The 13Th Research Institute of China Electronics Technology Group Corporation

The 13Th Research Institute of China Electronics

The 13Th Research Institute of China Electronics Technolegy Group Corporation

Yulong Fang

Zhihong Feng

Yuanjie Lv

Yuangang Wang

Xubo Song

Xin Tan

Xingye Zhou

Jia Li

Bo Wang

Hongyu Guo

Weili Lu

Jiayun Yin

Yanmin Guo

Zhirong Zhang

Guodong Gu

Shujun Cai

The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Method for manufacturing tilted mesa and method for manufacturing detector

A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Method for preparing avalanche photodiode

The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.

Silicon carbide detector and preparation method therefor

The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiOdielectric layer, thereby reducing device fabrication procedures.

Method for passivating silicon carbide epitaxial layer

An enhanced HFET, comprising a HFET device body. Regions without two-dimensional electron gas are provided on a channel layer () at the portion between a drain electrode () and a source electrode () of the HFET device body, and there is a region without two-dimensional electron gas provided on the channel layer () at the portions excluding the area under a gate electrode (); two-dimensional electron gas regions are provided on the channel layer () excluding the portions located between the drain electrode () and the source electrode () and provided with the regions without two-dimensional electron gas; the channel layer () at the portion between the gate electrode () and the source electrode () and the portion between the gate electrode () and the drain electrode () are each provided with a two-dimensional electron gas region; and two-dimensional electron gas () is provided at a portion or whole portion of a two-dimensional electron gas layer at the channel layer () at the portion right under the gate electrode (). The HFET has the advantages of high saturation current, high threshold voltage controllability, fast response, low energy consumption, and the like.

Enhanced HFET

Growing community of inventors

Shijiazhuang, China

Yulong Fang