Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Hitachi Power Semiconductor Device, Ltd.

Trecenti Technologies, Inc.

Yukihiro Kumagai

Hiroyuki Ohta

Hideo Miura

Tomio Iwasaki

Shuji Ikeda

Isamu Asano

Shingo Nasu

Masahiko Hiratani

Yuichi Matsui

Shinpei Iijima

Toshifumi Takeda

Yuzuru Ohji

Michihiro Mishima

Masato Kunitomo

Katsuyuki Nakanishi

Masahiro Moniwa

Naotaka Tanaka

Norio Ishitsuka

Fumio Ootsuka

Michiaki Hiyoshi

Takahiro Onai

Katsuhiko Ichinose

Masahiko Fujisawa

Akihiko Ohsaki

Yasuo Sonobe

Kousuke Ishibashi

Yasushi Tainaka

Masafumi Miyamoto

In a semiconductor device where a metal circuit layer is disposed over a main planar surface of an insulating substrate, a semiconductor chip is connected by way of a solder over the metal circuit layer, and a metal wiring is connected over the metal circuit layer, in which a solder flow prevention area comprising a linear oxide material is formed between the semiconductor chip and the ultrasonic metal bonding region over the metal circuit layer.

Semiconductor device and a method of manufacturing same

In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

Semiconductor device

The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.

Semiconductor device and manufacturing method thereof

A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.

Semiconductor device including active regions and gate electrodes for field effect transistors, with a trench formed between the active regions

The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.

Semiconductor device and manufacturing method

A semiconductor device which, even when a vertical transistor is adopted, is able to prevent a product yield from decreasing and performance from deteriorating, and at the same time, to achieve high-density integration of chips and high performance. The semiconductor device includes: a semiconductor substrate; a tower-like gate pillar formed on the semiconductor substrate via an insulation layer and including a channel region formed so as to be positioned between impurity diffusion regions in a vertically extended direction with respect to a principal side of the substrate; a gate insulation film formed on an outer surface of the gate pillar; and a gate electrode film including multiple conductive layers formed on an outer surface of the gate insulation film.

Semiconductor device with a vertical transistor

In a semiconductor device including n-channel field-effect transistors and p-channel field-effect transistors, in which the channel direction is parallel to a axis, a semiconductor device in provided which has excellent drain current characteristics at both n-channel field-effect transistors and p-channel field-effect transistors. In a semiconductor device including n-channel field-effect transistors Nand Nand p-channel field-effect transistors Pand P, a stress control film that covers the gate electrodes of the n-channel and p-channel field-effect transistors from upper surfaces thereof is not formed, or is made thin, above shallow trench isolations adjacent to active regions formed by the p-channel field-effect transistors Pand P, in a case where the stress control film is a tensile film stress. Thus, improvement of the drain currents of both the n-channel and p-channel transistors can be expected. For this reason, it is possible to improve overall characteristics.

Semiconductor device including n-channel fets and p-channel fets with improved drain current characteristics

In semiconductor devices, a semiconductor device is provided which is high in reliability while suppressing changes in characteristics such as threshold voltages. In a semiconductor device which has a gate dielectric film above a semiconductor substrate and also has above the gate dielectric film a gate electrode film made of silicon germanium chosen as its main constituent material, or alternatively in a semiconductor device which has beneath the gate dielectric film a channel made of silicon as its main constituent material and which has below the channel a channel underlayer film made of silicon germanium as its main constituent material, a specifically chosen dopant, such as cobalt (Co) or carbon (C) or nitrogen (N), is added to the gate electrode and the channel underlayer film, for use as the unit for suppressing diffusion of germanium in the gate electrode or in the channel underlayer film.

Semiconductor device configured for suppressed germanium diffusion from a germanium-doped regions and a method for fabrication thereof

The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistorand a p-channel field effect transistor, a stress control filmcovering a gate electrodeof the n-channel field effect transistorundergoes film stress mainly composed of tensile stress. A stress control filmcovering a gate electrodeof the p-channel field effect transistorundergoes film stress mainly caused by compression stress compared to the filmof the n-channel field effect transistor. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.

Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics

It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

Semiconductor device including storage capacitor

A semiconductor device is provided including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active area in which the transistor is formed). By such composition, stress growing in the active area due to the shallow trench isolation is equalized among the transistors, and, thereby, the characteristics of the transistors can be equalized.

A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

CAPACITOR STRUCTURE AND A SEMICONDUCTOR DEVICE WITH A FIRST METAL LAYER, A SECOND METAL SILICIDE LAYER FORMED OVER THE FIRST METAL LAYER AND A SECOND METAL LAYER FORMED OVER THE SECOND METAL SILICIDE LAYER

Semiconductor device with copper wiring connected to storage capacitor

METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS

Growing community of inventors

Chiyoda, Japan

Yukihiro Kumagai