Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Yuichi Matsui

Masahiko Hiratani

Yasuhiro Shimamoto

Toshihide Nabatame

Norikatsu Takaura

Nozomu Matsuzaki

Yoshitaka Nakamura

Naoki Yamamoto

Motoyasu Terao

Takao Watanabe

Satoru Akiyama

Shinpei Iijima

Yuzuru Ohji

Tomio Iwasaki

Hideyuki Matsuoka

Kenzo Kurotsuchi

Takahiro Morikawa

Hiroyuki Ohta

Hiroshi Miki

Yoshihisa Fujisaki

Kazuo Nojiri

Takashi Yunogami

Sukeyoshi Tsunekawa

Yukihiro Kumagai

Masato Kunitomo

Satoshi Yamamoto

Masaharu Kinoshita

Hiroshi Sakuma

Toshio Ando

Osamu Tonomura

Naruhiko Nakanishi

Tomoko Sekiguchi

Kikuo Watanabe

Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

Semiconductor memory

On an insulating film () in which a plug () as a lower electrode is embedded, a laminated layer pattern of an insulating film () made of tantalum oxide, a recording layer () made of Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced and an upper electrode film () made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film () between the recording layer () and the plug (), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer () can be achieved. Further, by using the Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced as the recording layer (), the difference in work function between the insulating film () and the recording layer () is increased, and the programming voltage of the phase change memory can be reduced.

Semiconductor device

A memory cell capacitor (C) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

Semiconductor device having plural DRAM memory cells and a logic circuit and method for manufacturing the same

A semiconductor device having a phase-change memory cell comprises an interlayer dielectric film formed of, for example, SiOF formed on a select transistor formed on a main surface of a semiconductor substrate, a chalcogenide material layer formed of, for example, GeSbTe extending on the interlayer dielectric film, and a top electrode formed on the chalcogenide material layer. A fluorine concentration in an interface between the interlayer dielectric film and the chalcogenide material layer is higher than a fluorine concentration in an interface between the chalcogenide material layer and the top electrode.

Semiconductor device with fluorine-containing interlayer dielectric film to prevent chalcogenide material layer from exfoliating from the interlayer dielectric film and process for producing the same

A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

Semiconductor device with recording layer containing indium, germanium, antimony and tellurium

The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600&#xb0; C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Capacitive electrode having semiconductor layers with an interface of separated grain boundaries

HfOfilms and ZrOfilms are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfOor ZrOwith an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Semiconductor memory device

Disclosed herein is a phase change memory semiconductor integrated circuit device using a chalcogenide film that solves a problem that the operation temperature capable of ensuring long time memory retention is low due to low phase change temperature is and, at the same time, a problem that power consumption of the device is high since a large current requires to rewrite memory information due to low resistance. A portion of constituent elements for a chalcogenide comprises nitride, oxide or carbide which are formed to the boundary between the chalcogenide film and a metal plug as an underlying electrode and to the grain boundary of chalcogenide crystals thereby increasing the phase change temperature and high Joule heat can be generated even by a small current by increasing the resistance of the film.

Semiconductor integrated circuit device and method of manufacturing the same

The annealing process at 400&#xb0; C. or more required for the wiring process for a phase change memory has posed the problem in that the crystal grains in a chalcogenide material grow in an oblique direction to cause voids in a storage layer. The voids, in turn, cause peeling due to a decrease in adhesion, variations in resistance due to improper contact with a plug, and other undesirable events. After the chalcogenide material has been formed in an amorphous phase, post-annealing is conducted to form a (111)-oriented and columnarly structured face-centered cubic. This is further followed by high-temperature annealing to form a columnar, hexagonal closest-packed crystal. Use of this procedure makes it possible to suppress the growth of inclined crystal grains that causes voids, since crystal grains are formed in a direction perpendicular to the surface of an associated substrate.

Semiconductor and semiconductor manufacturing arrangements having a chalcogenide layer formed of columnar crystal grains perpendicular to a main substrate surface

Semiconductor device having plural dram memory cells and a logic circuit

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Koganei, Japan

Yuichi Matsui