Applied Materials, Inc.

Novellus Systems Incorporated

Applied Komatsu Technology, Inc.

Stmicroelectronics S.r.l.

Yuh-Jia (Jim) Su

Kam S Law

Yuen-Kui (Jerry) Wong

David L Chen

Graham W Hills

Simone Alba

Senzi Li

Simona Petroni

Haruhiro (Harry) Goto

Giuseppe Colangelo

Eddie Ka Ho Chiu

Maria Paola Pozzoli

Shamouil Shamouilian

John F Cameron

Chandra V Deshpandey

Eddie Chiu

Cindy Wailam Chen

Anand Gupta

Haruhiro Harry Goto

Yoshiaki Tanase

Robert E Ryan

Joseph Lanucha

Wesley Phillip Graff

Richard C Muh

Vincent Bernard Decaux

Mavis J Chaboya

The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF, generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

Method for post-etch cleans

The current invention provides methods for performing a cleaning process that provides greater cleaning efficiency with less damage to device structures. After etching and photoresist stripping, a first plasma clean is performed. The first plasma clean may comprise one or more steps. Following the first plasma clean, a first HO based clean is performed. The first HO based clean may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. Following the first HO based clean, a second plasma clean is performed, which may comprise one or more steps. A second HO based clean follows the second plasma clean, and may be a de-ionized water rinse, a water vapor clean, or a plasma clean, where the plasma includes hydrogen and oxygen. For plasma processes, an RF generated plasma, a microwave generated plasma, an inductively coupled plasma, or combination may be used. Embodiments of the invention are performed after an etch, such as a metal etch, via etch, contact etch, polysilicon etch, nitride etch or shallow trench isolation etch has been performed. Photoresist may be removed either prior to, during, or after cleaning processes according to embodiments of the invention, using an oxygen-containing plasma. Photoresist removal may be performed at low temperatures.

Methods for post etch cleans

A method is disclosed for removing a polysilicon layer from a semiconductor wafer, in which a downstream plasma source is used first to planarize the wafer, removing contours in the polysilicon layer caused by deposition over lithographic features, such as via holes. The planarizing process is followed by exposure to a plasma made by a direct, radio frequency plasma source, which may be in combination with the downstream plasma source, to perform the bulk etching of the polysilicon. The invention can produce planar surface topography after the top layer of the film is removed, in which the residual recess height of the polysilicon plug filling a via hole is less than about about 10 nm.

Etch back process approach in dual source plasma reactors

The present invention pertains to methods for cleaning semiconductor wafers, more specifically, for removing polymeric and other residues from a wafer using dry plasmas generated with microwave (MW), electromagnetic field (inductively-coupled plasma (ICP)), and radio frequency (RF) energy. First, a wafer is treated by applying a microwave-generated plasma or an inductively-coupled plasma. Second, a radio frequency generated plasma is applied. Each of the microwave-generated plasma and the inductively-coupled plasma is produced from a gas mixture, which includes an oxygen source gas, a fluorine source gas, and a hydrogen source gas. Using such plasmas provides more controllable etch rates than conventional plasmas via control of fluorine concentration in the plasma. Application of a radio frequency generated (preferably oxygen-based) plasma is used for additional photoresist and polymer removal. The use of this two-step approach provides superior wafer cleaning compared to conventional wet and dry clean methods.

Methods for post polysilicon etch photoresist and polymer removal with minimal gate oxide loss

A plasma source for use in, for example, semiconductor processing contains a radio-frequency generator, an impedance matching network, and a coil that encloses a tube. The coil is bifilar, i.e., the turns of one are interlaced with the turns of a second winding. The matching network supplies only a single coil in the plasma source, unlike conventional arrangements wherein a single matching network supplies multiple coils in the plasma source.

Single-tube interlaced inductively coupling plasma source

The invention improves etch uniformity across a silcon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

Plasma reactor with enhanced plasma uniformity by gas addition, reduced

A method of forming an electrostatic chuck 20 for holding substrates 42 in a process chamber 40 containing a magnetic flux 43 is described. The method comprises the steps of forming a base 22 for supporting a substrate 42. An insulator 26 with an electrode 24 therein, is formed on the base 22. A magnetic shunt 34 comprising a ferromagnetic material is formed either (i) on the base 22, or (ii) in the insulator 26, or (iii) directly below, and contiguous to, the base 22.

Method of forming an electrostatic chuck suitable for magnetic flux

A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

Tapered dielectric etch in semiconductor devices

A method of etching an article having a substrate, an etchable film and a mask layer having a pattern formed therein includes the step of exposing the article to an etchant gas mixture which includes a halogen-containing gas and an inert gas. An etching profile is formed which is substantially smooth across an interface between the etchable film and the mask layer. The method is particularly useful in producing components of articles such as flat-panel displays.

Tapered profile etching method

An RIE method and apparatus for etching through the material layer of a transparent-electrode (ITO) in a single continuous step at a rate better than 100 .ANG./min and with a selectivity better than 20 to 1 is disclosed. Chamber pressure is maintained at least as low as 60 mTorr. A reactive gas that includes ethyl iodide C.sub.2 H.sub.5 I) is used alone or in combination with another gas such as O.sub.2. Plasma-induced light emissions of reaction products and/or the reactants are monitored to determine the time point of effective etch-through.

Dry-etch of indium and tin oxides with C2H5I gas

The invention improves etch uniformity across a silicon wafer surface in an RF plasma etch reactor. In a first aspect of the invention, etch uniformity is enhanced by reducing the etchant species (e.g., Chlorine) ion and radical densities near the wafer edge periphery without a concomitant reduction over the wafer center, by diluting the etchant (Chlorine) with a diluent gas which practically does not etch Silicon (e.g., Hydrogen Bromide) near the wafer edge periphery. In a second aspect of the invention, etch rate uniformity is enhanced by more rapidly disassociating Chlorine molecules over the center of the wafer to increase the local etch rate, without a concomitant hastening of Chlorine dissociation near the wafer periphery, by the introduction of an inert gas over the wafer center. In a third aspect of the invention, etch rate uniformity is enhanced by forcing gas flow from the gas distribution plate downward toward the wafer center to provide a greater concentration of Chlorine ions over the wafer center, by reducing the effective diameter of the chamber between the gas distribution plate and the wafer to approximately the diameter of the wafer. In a fourth aspect of the invention, etch rate uniformity is enhanced by reducing RF power near the wafer edge periphery, by reducing the RF pedestal to a diameter substantially less than that of the wafer.

Plasma reactor with enhanced plasma uniformity by gas addition, and

In one aspect, the invention is embodied in a plasma reactor for processing a semiconductor wafer, the reactor having a pedestal focus ring surrounding the periphery of the wafer for reducing the process etch rate near the wafer periphery, and plural openings through the pedestal focus ring which permit passage therethrough of particulate contamination, thereby reducing accumulation of particulate contamination near the wafer periphery. In another aspect, in order to reduce corrosive wear of the chamber walls, a removable gas distribution focus ring shields the side walls of the plasma reactor from reactive gases associated with processing of the semiconductor wafer.

Focus ring for semiconductor wafer processing in a plasma reactor

An RIE method and apparatus for etching through the material layer of a transparent-electrode (ITO) in a single continuous step at a rate better than 80 .ANG./min is disclosed. Chamber pressure is maintained at least as low as 30 mTorr. A reactive gas that includes a halogen hydride such as HCl is used alone or in combination with another reactive gas such as Cl.sub.2. Plasma-induced light emissions of reaction products and/or the reactants are monitored to determine the time point of effective etch-through.

Growing community of inventors

Cupertino, CA, United States of America

Yuh-Jia (Jim) Su