National Yang Ming Chiao Tung University

Yueh-Chin Lin

Edward Yi Chang

Yi Chang

Chia-Hua Chang

Shih-Chien Liu

Chia-Hsun Wu

Po-Sheng Chang

Chung-Kai Huang

Ping-Cheng Han

Ting-En Hsieh

Wei-Hua Chieng

Shih-Hsuan Tang

Yu-Kong Chen

Edward-Yi Chang

Ting-En Shie

Ming-Yen Tsai

Lu-Che Huang

Huan-Chung Wang

Yun-Chi Wu

A method of manufacturing a semiconductor device includes providing a substrate. A channel layer is formed on the substrate. A barrier layer is formed on the channel layer. A source and a drain are formed on the barrier layer. A recess is formed in the barrier layer, in which the recess has a bottom surface, and a portion of the barrier underneath the recess has a thickness. A first dielectric layer is formed to cover the bottom surface of the recess. A charge trapping layer is formed on the first dielectric layer. A first ferroelectric material layer is formed on the charge trapping layer. A second dielectric layer is formed on the first ferroelectric material layer. A second ferroelectric material layer is formed on the second dielectric layer. A gate is formed over the second ferroelectric material layer.

Method of manufacturing semiconductor device

A semiconductor device includes a substrate, a channel layer, a barrier layer, a ferroelectric composite material layer, a gate, a source and a drain. The channel layer and the barrier layer having a recess are disposed on the substrate in sequence. The ferroelectric composite material layer including a first dielectric layer, a charge trapping layer, a first ferroelectric material layer, a second dielectric layer and a second ferroelectric material layer is disposed in the recess. The gate is disposed on the ferroelectric composite material layer. The source and the drain are disposed on the barrier layer.

Semiconductor device and method of manufacturing the same

A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.

Method of fabricating transistor with short gate length by two-step photolithography

A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.

Process for making interconnect of group III-V semiconductor device, and group III-V semiconductor device including interconnect made thereby

An enhanced GaN transistor is provided. The structure comprises a substrate, a heterostructure, a p-element epitaxy growth layer, a drain ohmic contact and a source ohmic contact disposed on the heterostructure and on two sides of the p-element epitaxy growth layer, a gate structure disposed on the p-element epitaxy growth layer, and is separated from the drain ohmic contact and the source ohmic contact, a surface passivation layer covered the drain ohmic contact, source ohmic contact, and p-element epitaxy growth layer, and covered portion of the gate structure.

Enhanced GaN transistor and the forming method thereof

A structure of high electron mobility transistor growth on Si substrate and the method thereof, in particular used for the semiconductor device manufacturing in the semiconductor industry. The UHVCVD system was used in the related invention to grow a Ge film on Si substrate then grow the high electron mobility transistor on the Ge film for the reduction of buffer layer thickness and cost. The function of the Ge film is preventing the formation of silicon oxide when growing III-V MHEMT structure in MOCVD system on Si substrate. The reason of using MHEMT in the invention is that the metamorphic buffer layer in MHEMT structure could block the penetration of dislocation which is formed because of the very large lattice mismatch (4.2%) between Ge and Si substrate.

Structure of high electron mobility transistor growth on Si substrate and the method thereof

A semiconductor device includes a main body made of a GaN-based semiconductor material, and at least one electrode structure. The electrode structure includes an ohmic contact layer that is formed on the main body, a buffer layer that is formed on the ohmic contact layer opposite to the main body, and a circuit layer that is made of a copper-based material and that is formed on the buffer layer opposite to the ohmic contact layer. The ohmic contact layer is made of a material selected from titanium, aluminum, nickel, and alloys thereof. The buffer layer is made of a material different from the material of the ohmic contact layer and selected from titanium, tungsten, titanium nitride, tungsten nitride, and combinations thereof.

Semiconductor device

A hafnium oxide layer, between a III-V semiconductor layer and a metal oxide layer is used to prevent interaction between the III-V semiconductor layer and the metal oxide layer.

III-V metal-oxide-semiconductor device

A method for forming a T-shaped gate is provided. The method includes providing a substrate. Then, a photoresist structure is formed over the substrate. The photoresist structure includes two development rates. Next, a mask with an opening is formed over the photoresist structure to pattern the photoresist structure. An angle exposure is applied to the photoresist structure, and the exposed photoresist structure is developed to form a T-shaped notch. A width of the T-shaped notch is gradually reduced from a top portion thereof to a bottom portion to expose a surface of the substrate. Then, a gate metal is deposited in the T-shaped notch. Thereafter, the patterned photoresist structure is removed to form the T-shaped gate.

Method for forming T-shaped gate structure

A method for fabricating a GaN-based thin film transistor includes: forming a semiconductor epitaxial layer on a substrate, the semiconductor epitaxial layer having a n-type GaN-based semiconductor material; forming an insulating layer on the semiconductor epitaxial layer; forming an ion implanting mask on the insulating layer, the ion implanting mask having an opening to partially expose the insulating layer; ion-implanting a p-type impurity through the opening and the insulating layer to form a p-doped region in the n-type GaN-based semiconductor material, followed by removing the insulating layer and the ion implanting mask; forming a dielectric layer on the semiconductor epitaxial layer; partially removing the dielectric layer; forming source and drain electrodes; and forming a gate electrode.

Method for fabricating a GaN-based thin film transistor

Disclosed herein are a structure of a metal oxide semiconductor pseudomorphic high electron mobility transistor (MOS-PHEMT) suitable for use in a semiconductor device, such as a single-pole-double-throw (SPDT) switch of a monolithic microwave integrated circuit (MMIC); and a method of producing the same. The MOS-PHEMT structure is characterized in having a gate dielectric layer formed by atomic deposition from a gate dielectric selected from the group consisting of AlO, HfO, LaO, and ZrO, and thereby rendering the semiconductor structure comprising the same, such as a high frequency switch device, to have less DC power loss, less insertion loss and better isolation.

Growing community of inventors

Taipei, Taiwan

Yueh-Chin Lin