Advanced Micro Devices Corporation

Spansion Llc.

Promos Technologies, Inc

Intel Corporation

Other

Fujitsu Corporation

Altera Corporation

Kilopass Technology, Inc.

Yue-Song He

Richard M Fastow

Zhigang Wang

Kent Kuohua Chang

Sameer S Haddad

Andy Louie Lee

Nian Niles Yang

Jeffrey T Watt

Chi K Chang

Timothy J Thurgate

Richard G Smolen

Christopher J Pass

Rusli Kurniawan

Len Mei

Mark S Chang

Hao Fang

Effiong Etukudo Ibok

Jiahua Huang

Kazuhiro Mizutani

Jianshi Wang

Zhi-Gang Wang

Allen U Huang

Angela Tai Hui

Yu Nan Sun

Yowjuang William Liu

Xin Sheng Guo

Hung-Sheng Chen

Tatsuya Kajita

Imran Khan

Jun Kang

Takao Akaogi

Mark W Randolph

Jin-Ho Kim

John JianShi Wang

Pau-Ling Chen

Harry Luan

Narbeh Derhacobian

Wei Zheng

John S Foster

Ting-Wah Wong

Ming Sang Kwan

Che-Hoo Ng

Chung Wai Leung

Tat Hin Tan

Masaaki Higashitani

Nga-Ching Wong

Sheung-Hee Park

Choong Kit Wong

Kelwin Ko

Sheunghee Park

Pavel Fastenko

Wing Leung

Alok Nandini Roy

Kwok Kwok Ng

Sungchul Lee

Wing-Han Leung

Ngaching Wong

Frank Mak

Anwen Liu

Zheng Wei

Maria Chow-Chan

Bill Cox

Peter John Mcelheny

Integrated circuits with an array of programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive memory elements connected in series and two varistors. A first of the two varistors is used to program a top resistive memory element in the resistive switch element, whereas a second of the two varistors is used to program a bottom resistive memory element in the resistive switch element. Row and column drivers implemented using only thin gate oxide transistors are used to program a selected resistive switch in the array without violating a maximum voltage level that satisfies predetermined defects per million (DPM) reliability criteria.

Methods and circuitry for programming non-volatile resistive switches using varistors

Integrated circuits with programmable resistive switch elements are provided. A programmable resistive switch element may include two non-volatile resistive elements connected in series and a programming transistor. The programmable resistive switch elements may be configured in a crossbar array and may be interposed within the user data path. Driver circuits may also be included for selectively turning on or turning off the switches by applying positive and optionally negative voltages.

Integrated circuits with programmable non-volatile resistive switch elements

Integrated circuits with memory elements are provided. A memory element may include non-volatile resistive elements coupled together in a back-to-back configuration or an in-line configuration. Erase, programming, and margining operations may be performed on the resistive elements. Each of the resistive memory elements may receive a positive voltage, a ground voltage, or a negative voltage on either the anode or cathode terminal.

Integrated circuits with complementary non-volatile resistive memory elements

An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit enables the second transistor leg to generate the output signal at the output pad and disables the first transistor leg during a second phase of the cycle. The control circuit repeats the first and the second phases of the cycle.

Techniques for enabling and disabling transistor legs in an output driver circuit

The present invention provides an apparatus and method for a metal oxide semiconductor field effect transistor (MOSFET) fabricated to reduce short channel effects. The MOSFET includes a semiconductor substrate, a gate stack formed above the semiconductor substrate, a drain side sidewall spacer formed on a drain side of the gate stack, a source side sidewall spacer formed on a source side of the gate stack, and source and drain regions. The source region is formed in the semiconductor substrate on the source side, and is aligned by the source side sidewall spacer to extend an effective channel length between the source region and drain region. The drain region is formed on the drain side in the semiconductor substrate, and is aligned by drain side sidewall spacer to further extend the effective channel length.

Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors

A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.

One-time programmable memory and method for making the same

A memory device includes a cell stack and a select gate formed adjacent to the cell stack. The cell stack includes a tunneling dielectric layer, a charge storage layer, a blocking dielectric layer, and a control gate. Applying a positive bias to the control gate, the select gate and the source of the device injects negative charges from a channel region of a substrate by hot electron injection through the tunneling dielectric layer at a location near a gap between the select gate and the control gate into the charge storage layer to store negative charges in the charge storage layer. Applying a negative bias to the control gate directly tunnels positive charges from the channel region of the substrate through the tunneling dielectric layer and into the charge storage layer to store positive charges in the charge storage layer.

Non-volatile memory devices with charge storage regions

Charge-trapping dielectric () in a nonvolatile memory cell is recessed from under the control gate's edge and/or from an edge of a substrate isolation region. The recessed geometry serves to reduce or eliminate charge trapping in regions from which the charge may be difficult to erase.

Nonvolatile memories with laterally recessed charge-trapping dielectric

A floating gate memory cell's channel region () is at least partially located in a fin-like protrusion (P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric () separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer () and then forming spacers () from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer () is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.

Integrated circuits with substrate protrusions, including (but not limited to) floating gate memories

A memory cell () has a plurality of floating gates (L,R). The channel region () comprises a plurality of sub-regions (L,R) adjacent to the respective floating gates, and a connection region () between the floating gates. The connection region has the same conductivity type as the source/drain regions () to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric () becomes thick between the floating gates, weakening the control gate's () electrical field in the channel.

Nonvolatile memory cell with multiple floating gates and a connection region in the channel

A flash memory cell and a method of forming the same are described. The flash memory cell may include a substrate having a source and a drain, a gate element, and a dielectric layer between the substrate and the gate element. The dielectric layer includes a dielectric material having a dielectric constant that is greater than that of silicon dioxide.

Flash memory with high-K dielectric material between substrate and gate

The present invention provides a method for determining program and erase states in flash memory devices. Specifically, one embodiment of the present invention discloses a method for minimizing false detection of states in an array of non-volatile floating gate memory cells. A plurality of word lines are arranged in a plurality of rows. A plurality of bit lines are arranged in a plurality of columns. The method begins by determining a selected bit line that is associated with a column of memory cells. Then, the method continues by biasing a group of word lines at a negative voltage. The group of word lines are electrically coupled to the associated memory cells. The application of negative voltage to the group of word lines limits leakage current contributions from the associated memory cells in the column of memory cells when performing a verify operation.

Method for minimizing false detection of states in flash memory devices

A method for fabricating a semiconductor device having improved short channel effects is disclosed. The method includes operations such as, forming a hard mask layer on the surface of a semiconductor substrate, printing a photoresist mask above the hard mask layer, performing an etch of trenches in the semiconductor substrate and removing the hard mask layer and the photoresist mask. Moreover, the method includes forming a first polysilicon layer, etching the first polysilicon layer, forming a spacer layer and forming a second polysilicon layer. In addition, the method includes performing a stacked gate etch on the second polysilicon layer, performing an SAS etch, performing a shallow source implant and forming the spacer between the first polysilicon layer and the second polysilicon layer. A silicide line is subsequently formed to connect device source regions.

Method for providing short channel effect control using a silicide VSS line

Growing community of inventors

San Jose, CA, United States of America

Yue-Song He