Applied Materials, Inc.

Cabot Microelectronics Corporation

Asm Nutool, Inc.

Nutool, Inc.

Yuchun Wang

Stan D Tsai

Fred Conrad Redeker

Rajeev Bajaj

Liang-Yuh Chen

Feng Quan Liu

Yan Wang

Alain Duboust

Wen-Chiang Tu

Manoocher Birang

Paul D Butterfield

Rashid Mavliev

Ralph M Wadensweiler

Daniel A Carl

Boguslaw A Swedek

Kun Xu

Lakshmanan Karuppiah

You Wang

Kapila P Wijekoon

Dominic J Benvegnu

Douglas W Young

Efrain A Velazquez

Bulent Mehmet Basol

Homayoun Talieh

Robert A Ewald

Laksh Karuppiah

Mukesh Desai

Brett E McGrath

Hung Chih Chen

Shijian Li

Brian J Brown

Barry Lee Chin

Shou-Sung Chang

Wei-Yung Hsu

Lizhong Sun

Jui-lung Li

Doyle E Bennett

Madhavi R Chandrachood

Heinz Hermann Busta

Ingemar Carlsson

Abraham Ravid

Bernard Frey

Siew Neo

David Maxwell Gage

John C Parker

David Schroeder

Renjie Zhou

Jie Diao

Renhe Jia

Ian Wylie

William H McClintock

Tuan Truong

J Scott Steckenrider

Bernard M Frey

Jason Aggio

Bin Lu

Pierre Fontarensky

Liang-Yun Chen

John Parker

During polishing of a first substrate at a first polishing station, a sequence of measurements by a first in-situ monitoring system is monitored to determining a first time at which the first sequence exhibits a first predefined feature indicating a predetermined thickness of an overlying layer, and during polishing of the first substrate at a second polishing station, a sequence of measurements by a second in-situ monitoring system is monitored to determine a second time indicating clearance of the overlying layer and exposure of the underlying layer. The first time is used to calculate a first adjusted polishing pressure for a second substrate at the first polishing station, and the second time is used to calculate a second adjusted polishing pressure for the second substrate at the second polishing station.

Feedback of layer thickness timing and clearance timing for polishing control

A method of controlling polishing includes polishing a first substrate having an overlying layer on an underlying layer or layer structure. During polishing, the substrate is monitored with an in-situ monitoring system to generate a sequence of measurements. The measurements are sorted into groups, each group associated with a different zone of a plurality of zones on the substrate. For each zone, a time at which the overlying layer is cleared is determined based on the measurements from the associated group. At least one second adjusted polishing pressure for at least zone is calculated based on a pressure applied in the at least one zone during polishing the substrate, the time for the at least one zone, and the time for another zone. A second substrate is polished using the at least one adjusted polishing pressure.

Feedback control of polishing using optical detection of clearance

In polishing a substrate having a layer of GST disposed over an underlying layer, during polishing, a non-polarized light beam is directed onto the layer of GST. The non-polarized light beam reflects from the first substrate to generate a reflected light beam having an infra-red component. A sequence of measurements of intensity of the infra-red component of the reflected light beam are generated, and, in a processor, a time at which the sequence of measurements exhibits a predefined feature is determined.

GST film thickness monitoring

Methods of determining thickness and phase of a GST layer on a semiconductor substrate are described using intensity spectra within the infra-red range. In particular, techniques for using certain transmission at certain frequencies are disclosed for faster thickness and phase determination in an in-line or standalone metrology/monitoring system for CMP processes.

Metrology for GST film thickness and phase

Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarizing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer.

Chemical planarization of copper wafer polishing

A chemical mechanical polishing apparatus includes a metrology system that detects the thickness of the polishing pad as semiconductor wafers are processed and the thickness of the polishing pad is reduced. The chemical mechanical polishing apparatus includes a controller that adjusts the rate of material removal of a conditioning disk when areas of the polishing surface are detected that are higher or lower than the adjacent areas of the polishing pad.

Closed loop control of pad profile based on metrology feedback

A method and apparatus for polishing or planarizing a substrate by a chemical mechanical polishing process. In one embodiment a method of processing a semiconductor substrate is provided. The method comprises positioning a substrate on a polishing apparatus comprising a polishing pad assembly, delivering a polishing slurry to a surface of the polishing pad assembly, polishing the substrate with the surface of the polishing pad assembly, monitoring the removal rate of material from a plurality of regions on the surface of the substrate, determining whether the plurality of regions on the surface of the substrate are polishing uniformly, and selectively delivering a polishing slurry additive to at least one region of the plurality of regions to obtain a uniform removal rate of material from the plurality of regions on the surface of the substrate, wherein the removal rate of material from the at least one region is different than at least one other region of the plurality of regions.

Dishing and defect control of chemical mechanical polishing using real-time adjustable additive delivery

A method and apparatus for extending a polishing article lifetime on a polishing tool with multiple platens is described. The apparatus includes an advanceable roll to roll platen with multiple embodiments of a polishing article to be used thereon. The polishing article is adapted to perform a polishing process by removing conductive and dielectric material from a substrate while minimizing downtime of the polishing tool. In some embodiments, the polishing article may be a dielectric material or a conductive material and is configured to include a longer usable lifetime to minimize replacement and downtime of the tool.

Extended pad life for ECMP and barrier removal

The invention provides compositions and methods for planarizing or polishing a surface. One composition comprises about 0.01 wt. % to about 20 wt. % &#x3b1;-alumina particles, wherein the &#x3b1;-alumina particles have an average diameter of 200 nm or less, and 80% of the &#x3b1;-alumina particles have a diameter of about 500 nm or less, an organic acid, a corrosion inhibitor, and water. Another composition comprises &#x3b1;-alumina particles, an organic acid, dual corrosion inhibitors of triazole and benzotriazole, wherein the wt. % ratio of the triazole to benzotriazole is about 0.1 to about 4.8, and water.

Composition and method for planarizing surfaces

An article of manufacture and apparatus are provided for processing a substrate surface. In one aspect, an article of manufacture is provided for polishing a substrate including polishing article comprising a body having at least a partially conductive polishing surface. An electrode is disposed below the polishing surface having a dielectric material therebetween. A plurality of apertures may be formed in the polishing surface and the dielectric material to at least partially expose the electrode to the polishing surface. A membrane may be disposed between the electrode and the polishing surface that is permeable to ions and current to promote continuity between the electrode and the polishing surface.

Conductive pad with ion exchange membrane for electrochemical mechanical polishing

An article of manufacture and apparatus are provided for planarizing a substrate surface. In one aspect, an article of manufacture is provided for polishing a substrate including polishing article comprising a body having at least a partially conductive surface adapted to polish the substrate. A plurality of perforations may be formed in the polishing article for flow of material therethrough. An electrode is also exposed to the polishing surface by at least a portion of the plurality of perforations. The article of manufacture may also include a polishing surface having a plurality of grooves, wherein a portion of the plurality of grooves intersect with a portion of the plurality of perforations.

Conductive polishing article for electrochemical mechanical polishing

An article of manufacture and apparatus are provided for planarizing a substrate surface. In one aspect, an article of manufacture is provided for polishing a substrate including polishing article comprising a body having at least a partially conductive surface adapted to polish the substrate and a mounting surface. A plurality of perforations may be formed in the polishing article for flow of material therethrough. In another aspect, a polishing article for polishing a substrate includes a body having a polishing surface and a conductive element disposed therein. The conductive element may have a contact surface that extends beyond a plane defined by the polishing surface. The polishing surface may have one or more pockets formed therein. The conductive element may be disposed in each of the polishing pockets.

A three-dimensional integrated circuit that provides reduced interconnect signal delay over known 2-dimensional systems. The three-dimensional integrated circuit also allows improved circuit cooling. The three-dimensional integrated circuit includes two or more electrically connected integrated circuits, separated by a cooling channel.

Three dimensional integrated circuits

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San Jose, CA, United States of America

Yuchun Wang