Yangtze Memory Technologies Co., Ltd.

Yuanyuan Min

XiangNan Zhao

Jianquan Jia

Yali Song

Lei Jin

Kaikai You

Hongtao Liu

Ying Cui

Xuezhun Xie

Ying Huang

Shan Li

HongTao Liu

An Zhang

Kaiwei Li

Feng Xu

Xinlei Jia

Chenhui Li

Lei Guan

Junbao Wang

Shiyu Xia

Jie Yuan

Wei Qi

YaLi Song

Ting Cheng

WenZhe Wei

Tingze Wang

The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Memory devices and operating methods thereof, memory systems

A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.

Programming method for semiconductor device and semiconductor device

The present disclosure provides a method for erasing a memory device. The method includes applying a word-line voltage to a word line of the memory device, wherein a first set of memory cells coupled to the word line are each configured to store a first number of bits data. The method also includes applying a hold voltage to a selected dummy line for a first time period, wherein a second set of memory cells coupled to the selected dummy line are each configured to store a second number of bits data less than the first number of bits data. The method further includes removing the hold voltage from the selected dummy line after the first time period such that an electric potential of the selected dummy line rises to a first voltage higher than the word-line voltage; and increasing the first time period incrementally in each of subsequent erase loops.

Memory devices, operation method thereof and memory system

In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Method of improving program operation speed in 3D NAND systems

The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Method of reducing Vpass disturb in 3D nand systems

Upon determining that a first read operation on one memory cell of a plurality of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to first unselected word lines, and a first pass voltage is applied to second unselected word lines. The first unselected word lines include one or more word lines adjacent to a selected word line, and the second unselected word lines include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the first unselected word lines in the first read operation. The second pass voltage is higher than the first pass voltage.

Memory device, memory system, and read operation method thereof

A three-dimensional (3D) memory device includes a first set of word lines coupled to first memory cells, a second set of word lines coupled to second memory cells, an interface dummy word line between the first and send sets of word lines, and a peripheral circuit coupled to the first and send memory cells. The peripheral circuit is configured to apply a first voltage to the interface dummy word line in a first pre-charge period when programming a first selected memory cell in the first memory cells, and apply a second voltage lower than the first voltage to the interface dummy word line in a second pre-charge period when programming a second selected memory cell in the second memory cells. Programing the first selected memory cell is earlier than the second selected memory cell.

Three-dimensional memory device programming with reduced disturbance

A three-dimensional (3D) memory device and method for reading the same are provided. The device includes memory cell strings each including multiple memory cells. In each memory cell string, a topmost memory cell is connected to a top selection gate connected to a bit line, and a bottommost memory cell is connected to a bottom selection gate. The method includes sequentially programming multiple memory cells in a memory cell string according to a programming sequence; in reading a memory cell, applying a corresponding bit line voltage to the memory cell string according to the programming sequence of the memory cell.

Three-dimensional memory device and method for reading the same

The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage. The first pass voltage is applied to first non-selected memory cells in the first portion, and the second pass voltage is applied to second non-selected memory cells in the second portion.

Three-dimensional memory and control method thereof

A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.

A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.

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Wuhan, China

Yuanyuan Min