Texas Instruments Corporation

Agere Systems Inc.

Agere Systems Guardian Corp.

Microsol Technologies Inc.

Yuanning Chen

Pradip Kumar Roy

Sundar Srinivasan Chetlur

Nagarajan Sridhar

Sailesh Mansinh Merchant

Deborah J Riley

Maxwell Walthour Lippitt, Iii

William M Moller

Thomas Patrick Conroy

Mark R Visokay

Haowen Bu

Yi Ma

Antonio L P Rotondaro

Kaiping Liu

Jarvis Benjamin Jacobs

Stephanie Watts Butler

Jeffrey R Debord

Karen Kirmse

Karen H R Kirmse

Konstantin K Bourdelle

Jesus Israel Mejia Silva

Chunya Wu

Linette Lozada

Roger Morgan Young

Yun-Ju Lee

Jeffrey DeBord

MIM capacitors using low temperature sub-nanometer periodic stack dielectrics (SN-PSD) containing repeating units of alternating high dielectric constant materials sublayer and low leakage dielectric sublayer are provided. Every sublayer has thickness less than 1 nm (sub nanometer). The high dielectric constant materials could be one or more different materials. The low leakage dielectric materials could be one or more different materials. For the SN-PSD containing more than two different materials, those materials are deposited in sequence with the leakage current of the materials from the lowest to the highest and then back to the second-lowest, or with the energy band gap of the materials from the widest to the narrowest and then back to the second widest in each periodic cell. A layer of low leakage current dielectric materials is deposited on and/or under SN-PSD. The dielectric constant of SN-PSD is much larger than that of the component oxides and can be readily deposited at 250&#xb0; C. using atomic layer deposition (ALD). The ALD deposition cycle could be 20-1000 cycles. The deposition technology is not limited to ALD, could be thermal oxidation, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and other thermal source assisted deposition.

Low temperature sub-nanometer periodic stack dielectrics

A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the photovoltaic cell portion.

Self-powered integrated circuit with photovoltaic cell

A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.

Self-powered integrated circuit with multi-junction photovoltaic cell

A method for forming a metal silicide region in a silicon region of a semiconductor substrate. The method comprises forming a metal layer over the silicon region, then in succession forming a titanium and a titanium nitride layer thereover. As the substrate is heated to form the silicide, the titanium getters silicon dioxide on the surface of the silicon region and the titanium nitride promotes the formation of a smooth surface at the interface between the silicide layer and the underlying silicon region.

Integrated circuit with metal silicide regions

A method for manufacturing a semiconductor device. The method comprises depositing a material layer on a semiconductor substrate and patterning the material layer with a patterning material. Patterning forms a patterned structure of a semiconductor device, wherein the patterned structure has a sidewall with a roughness associated therewith. The method also comprises removing the patterning material from the patterned structure and annealing an outer surface of the patterned structure such that the roughness is reduced.

Annealing to improve edge roughness in semiconductor technology

A complementary metal oxide semiconductor (CMOS) device has a substrate, a gate structuredisposed atop the substrate, and spacers, deposited on opposite sides of the gate structureto govern formation of deep source drain regions S, D in the substrate. Spacersare formed of an oxynitride (SiONC) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate, forming a gate structureover the substrate, depositing a first layeratop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiONC) layeratop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layeratop the oxynitride layer, and depositing a nitride layerB atop the second layer.

Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

The present invention provides a method for manufacturing a semiconductor device, which includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.

Method for manufacturing a semiconductor device having improved across chip implant uniformity

A semiconductor device includes offset spacers that contact opposing side surfaces of a gate of a gate structure. The offset spacers can be formed by selectively depositing an oxide layer over the gate and the semiconductor substrate so that the opposing side surfaces of the gate e are substantially free of the oxide layer. Offset spacers can then be formed that contact the opposing side surfaces of the gate.

Reduction of dopant loss in a gate structure

Method for forming metal silicide regions in an integrated circuit

A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.

Process for oxide fabrication using oxidation steps below and above a threshold temperature

The present invention pertains to formation of a transistor in a manner that mitigates parasitic capacitance, thereby facilitating, inter alia, enhanced switching speeds. More particularly, a sidewall spacer formed upon a semiconductor substrate adjacent a conductive gate structure includes a material having a low dielectric constant (low-k) to mitigate parasitic capacitance between the gate structure, the sidewall spacer and a conductive drain formed within the semiconductor substrate. The low-k sidewall spacer is encapsulated within a nitride material which is selective to etchants such that the spacer is not altered during subsequent processing. The spacer thus retains its shape and remains effective to guide dopants into desired locations within the substrate.

Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology

A semiconductor device having improved dielectric properties and a method for fabricating a semiconductor device. A semiconductor device includes a semiconductor layer suitable for device formation. A dielectric layer formed over the semiconductor layer has first and second opposing surfaces, a first surface region along the first surface and a second surface region along the second surface. A mid region is positioned between the first and second surface regions. The material of the dielectric layer includes a species having a concentration greater in the mid region than along the first opposing surface. The dielectric layer may be incorporated in a field effect transistor or a capacitor. According to a disclosed method an insulative layer is formed with two or more elements chemically bonded to one another. An additional species is introduced into the insulative layer in sufficient quantity to modify the net dielectric constant of the layer.

Electronic circuit structure with improved dielectric properties

TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE

A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.

Growing community of inventors

Plano, TX, United States of America

Yuanning Chen