Via Technologies, Inc.

Yuan-Tsang Liaw

Chi-Hsing Hsu

Hsing-Chou Hsu

Hung-Wen Shih

A chip structure with a bevel pad row comprises a substrate, a plurality of middle pad rows, and a bevel pad row. The substrate has an active surface including a middle wire bonding area and a corner wire bonding area. The middle wire bonding area is adjacent to a side of the active surface. The corner wire bonding area is adjacent to the side and a end of the middle wire bonding area, and the corner wire bonding area has a bevel edge with an acute incline angle to the side. The middle pad rows are disposed in the middle wire bonding area, and the bevel pad row is disposed along the bevel edge of the corner wire bonding area. The bevel pad row has a plurality of bevel pads, and the quantity of which is greater than that of the middle pad rows in the middle wire bonding area.

Chip structure with bevel pad row

A chip structure includes a substrate with at least an arrangement of side pads on an active surface of the substrate and adjacent to one side of the active surface. The arrangement of side pads includes an outer pad row, a middle pad row and an inner pad row disposed along the extension direction of the side. The middle pad row is further away from the side than the outer pad row. The inner pad row is further away from the side than the middle pad row. Pads of the middle pad row and pads of the inner pad row are staggered. One non-signal pad of the middle pad row is located between two adjacent signal pads of the inner pad row, and one non-signal pad of the inner pad row is located between two adjacent signal pads of the middle pad row.

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Yuan-Tsang Liaw