Chipmos Technologies Inc.

Other

Chipmos Technologies (bermuda) Ltd

Yuan-Ping Tseng

An-Hong Liu

Yeong-Her Wang

Yao-Jung Lee

Shih-Jye Cheng

Y J Lee

S J Cheng

Vincent Wang

Linck Cheng

A method for fabricating an anisotropic conductive substrate is disclosed. A back holder has metal pins on a surface thereof. A liquid compound is formed on the surface of the back holder with metal pins. The liquid compound is pressed to deform the metal pins into electrodes in the liquid compound. The thickness between upper surface and lower surface of the liquid compound is between 25 &#x3bc;m and 250 &#x3bc;m. The electrodes have upper ends and lower ends exposed from upper surface and lower surface of the liquid compound to provide electrical contact of anisotropic conduction.

Method for fabricating anisotropic conductive substrate

A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of the probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.

Method for manufacturing probes of a probe card

A probe card assembly is disclosed. The probe card assembly comprises a stiffener ring combining respectively with an upper printed circuit board and a lower printed circuit board. A plurality of coaxial transmitters are installed in the stiffener ring, and connect to the upper and lower printed circuit boards by cable connectors. The lower printed circuit board is assembled with a detachable probe head which comprises a silicon substrate with probing points and a probe head carrier. A downset is formed at the center of the probe head carrier. The standardized coaxial transmitters, printed circuit boards and probe heads are then assembled as a probe card assembly for testing all sorts of IC products.

Probe card assembly

A modularized probe card with coaxial transmitter is disclosed. At least a coaxial transmitter is modularized and installed between a first printed circuit board and a second printed circuit board. The coaxial transmitter has a first connector and a second connector correspondingly connecting two ends of each coaxial cable of the coaxial transmitter for electrically connecting corresponding in location to first printed circuit board and second printed circuit board. A probe head is bonded on second printed circuit board. The second connector of the coaxial transmitter is connected with the second printed circuit board in a plug-in and pull-away type.

Modularized probe card with coaxial transmitters

A modularized probe card comprising an interface board, a probe head and at least a compressible electrical connection device is disclosed. The compressible electrical connection device comprises an insulation layer with a plurality of circuits on one of its surface. Two ends of each circuit connect respectively to the first contacting pad and the second contacting pad which combine with elastic contact members. Each elastic contact member has a supporter combining with a conductive layer for electrical connections by pushing and compressing. While a probe head is modularized installed on an interface board, the elastic contact members of the compressible electrical connection device is elastically contacted and compressed the probe head and the interface board to acquire modularized electrical connection of the probe card.

Modularized probe card with compressible electrical connection device

A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.

Method and system for performing memory repair analysis

A flip chip type semiconductor device for reducing signal skew includes: a chip with bonding pads, and a plurality of bumping pads on the chip. Between each bonding pad and corresponding bumping pads is connected with a metal redistribution trace covered by a passivation layer. Each metal trace has an equal trace length for reducing signal skew.

Flip-chip type semiconductor device for reducing signal skew

A modular probe card assembly comprises a silicon substrate with probes modularly assembled on a main board. At least a socket is installed around silicon substrate and electrically connects to probe needles by a flexible printed wiring film. A plurality of detachable coaxial wires electrically connect sockets with the main board for achieving variability of connecting paths during manufacturing. Thus, the probe card assembly has the effect of adjustable amendment and is suitable for high speed testing.

Modular probe card assembly

A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.

Wafer level packaging for making flip-chips

A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.

Semiconductor wafer designed to avoid probed marks while testing

A manufacturing process of semiconductor devices comprises providing at least a wafer, bumping the wafer, testing the wafer, laser repairing, and dicing. The step of testing one bumped wafer is contained after bumping and before laser repairing in order to shorten the procedures and increase throughput

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Hsinchu, Taiwan

Yuan-Ping Tseng