Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Yuan-Ko Hwang

Chun Hsiung Tsai

Fei-Yun Chen

Tsung-Chi Hsieh

Kuei-Jen Chang

Yuan-Pang Lee

Chi-Cherng Jeng

Hsin-Chi Chen

Ping-Hung Yin

Shih-Shiung Chen

Fu-Cheng Chang

Chih-Fei Lee

Hung-Hsin Liu

Hao-Chih Yuan

Chen-Shiang Shieh

Juei-Wen Lin

Ying-Chen Chao

Sen-Fu Chen

Yuh-Hwa Chang

Ching-Wen Cho

Huan-Wen Wang

How-Cheng Tsai

Kwang-Chen Wu

Shih-Shun Chen

Jen-Shian Shieh

Shih Chiung Chen

Jen-Yung Tseng

Ni-Hwi Kuan

Nan-Huan Kuan

Shuh-Shun Chen

Jeng Kuen Lu

Tsung Tser Lee

Yung-Sung Peng

The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Metal-insensitive epitaxy formation

The present disclosure provides a method forming a field effect transistor (FET) in accordance with some embodiments. The method includes performing an etching process to a semiconductor substrate, thereby forming recesses in source and drain (S/D) regions of the semiconductor substrate; forming a passivation material layer of a first semiconductor in the recesses; and epitaxially growing a second semiconductor material, thereby forming S/D features in the recesses, wherein the S/D features are separated from the semiconductor substrate by the passivation material layer.

A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90&#xb0;. Therefore, the step coverage of the later formed metal layer can be improved.

Method of forming redistribution layer

Under bump metallization

A new method is provided to create a polysilicon fuse. The invention provides for applying a first oxide plasma treatment to the surface of the created polysilicon fuse, creating a thin layer of native oxide over the surface of the created polysilicon fuse, followed by a DI water rinse. This thin layer of native oxide is made more robust by applying a second oxide plasma treatment to exposed surfaces, this more robust layer of native oxide protects the polysilicon fuse during subsequent processing steps of wet photoresist and polymer removal.

Semiconductor device with robust polysilicon fuse

A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.

Method to avoid amorphous-si damage during wet stripping processes in the manufacture of MEMS devices

The present subject matter relates to a method of stripping a photoresist after the photoresist film has been subjected to a high dose and high energy ion implant process. The method involves soaking the photoresist film in DI water, dry etching with oxygen plasma, and immersing in Caro's acid solution to improve the throughput of removing the film from the underlying substrate. The method can also be used to strip photoresist that has been hardened or altered by other types of processes such as dry etch transfer steps and chemical treatments. In some applications, the dry etching step may be omitted from the stripping process or the dry etching step may be combined with the water soak in an integrated process.

Effective photoresist stripping process for high dosage and high energy ion implantation

Method of fabricating a poly fuse

A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of 'write disturb', unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well-controlled dimensions and well-defined shapes through a judicious use of a fully wet etch technique, including main-etch and over-etch. The use of a phosphoric acid solution in combination with sulfuric acid+hydrogen peroxide widens the process window from a few seconds to several minutes so that the small-dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In the first embodiment phosphoric solution is used both for main-etch and for over-etch. In the second embodiment, phosphoric solution is used for main-etch only, while the sulfuric+hydrogen peroxide solution is used as an over-etch in forming the tiny silicon nitride spacers of the invention. In the third embodiment, the step of over-etching of the spacers is combined with the step of stripping off of an implant photomask, thus, shortening the manufacturing product cycle.

Method of forming tiny silicon nitride spacer for flash EPROM by fully wet etching technology

A method for in-situ descum/hot bake/dry etch a polyimide photoresist layer and a passivation layer in a singe process chamber is disclosed. A process chamber that can be used for conducting in-situ a descum, a hot bake and a dry etch process sequentially in the same chamber is also disclosed. In the method, a process chamber equipped with a wafer platform and a wafer backside heating and cooling device is first provided, followed by the step of positioning a wafer that has a passivation layer and a patterned polyimide photoresist layer on top of the platform. An oxygen plasma is then generated in the chamber cavity to conduct a descum process, followed by flowing a heated inert gas onto a backside of the wafer to conduct a hot bake process. A cooling inert gas is then flown onto the wafer backside and an etchant gas is flown into the chamber to conduct a dry etch process for forming a via opening in the wafer.

Method and apparatus for in-situ descum/hot bake/dry etch photoresist/polyimide layer

A method of forming very small silicon nitride spacers in split-gate flash EPROMs is disclosed which prevent the occurrence of &ldquo;write disturb&rdquo;, unwanted reverse tunneling, or erasing. This is accomplished by forming spacers with well controlled dimensions and well defined shapes through a judicious combination of dry etch with wet over-etch technique. The wet etch along with the dry etch widens the process window from a few seconds to several minutes so that the small dimensioned silicon nitride spacers can be better controlled than it has been possible in the past. In a second embodiment, the step of over-etching of the spacers is combined with the step of stripping off of an implant photomask, thus, shortening the manufacturing product cycle.

Method of forming tiny silicon nitride spacer for flash EPROM by using dry&plus;wet etching technology

A method for manufacturing capacitors is disclosed. The method is applicable to a capacitor whose upper electrode area is smaller than the lower electrode area. It is featured in that a material, such as a TiN hard mask, is inserted between the conventional electrode metal layer and photo resist layer. This enables one to perform the in-situ photo resist layer removal step after dry etching the upper electrode metal. Since the photo resist layer removal step uses oxygen plasma, the surface of the lower electrode polysilicon is formed with a protective oxide layer because the dielectric layer is etched during the process of dry etching the upper electrode metal. Using the disclosed method can solve the corrosion problem on the upper electrode metal and avoid the lower electrode polysilicon from being corroded by the wet etchant.

Method of making capacitors

A process for creating a fuse structure opening in a stack of materials comprised with overlying dielectric layers, and comprised with an underlying polysilicon layer, to expose a conductive fuse structure, has been developed. The process initiates with a dry etching procedure used to create an initial fuse structure opening in the dielectric layers, using a photoresist shape as an etch mask. Subsequent removal of the photoresist shape results in the completion of the fuse structure opening via in situ etching of the polysilicon layer exposed in the initial fuse structure opening. The isotropic wet etch procedure used for photoresist removal and in situ patterning of polysilicon, avoids polysilicon spacer formation on the sides of the conductive fuse structure, which would have been present with the use of an all dry etch procedure. In addition the wet etch procedure selectively terminates on a thin silicon oxide layer, located on the underlying conductive fuse structure.

Method of etching a polysilicon layer during the stripping of the photoresist shape used as an etch mask to create an opening to an underlying fuse structure

Growing community of inventors

Hualien, Taiwan

Yuan-Ko Hwang