Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Industrial Technology Research Institute

Yuan-Ching Peng

Jiun-Ming Kuo

Wei-Yang Lee

Chia-Pin Lin

Kuo-Yi Chao

Che-Lun Chang

You-Ting Lin

Yu-Shan Lu

Sung-En Lin

Chih-Chung Chang

Yu-Bey Wu

Jen-Hong Chang

Chung-Ting Ko

Yi-Hsiu Liu

Chia-Cheng Chao

Hung-Ju Chou

Shih-Chiang Chen

Yen-Po Lin

Yu-Fan Peng

Wen-Hsing Hsieh

Wei-Ming Chen

Hsien-Hsin Lin

Lih-Juann Chen

Shu-Wen Shen

Chung-I Yang

Chih-Han Lin

Shih-Yao Lin

Kuei-Yu Kao

Chun-Hsiung Tsai

Chien-Tai Chan

Sheng-Hsiung Wang

Chunyao Wang

Ting-Yeh Chen

Shyue-Shyh Lin

Pei-Yi Liu

Chih-Ching Wang

Hung-Kai Chen

Ji-Yin Tsai

Chi-Sheng Lai

Wei-Chung Sun

Yi-Cheng Li

Li-Ting Chen

Yong-Fen Hsieh

Shih-Hao Fu

Nung-Che Cheng

Jing Yi Yan

Hung-Jiu Chou

Chi On Chui

Chi-Hsi Wu

Yung-Cheng Lu

Fu-Kai Yang

Chien-Hung Chen

Pei-Ren Jeng

Chien-Chih Chen

Chi-Cheng Hung

Da-Wen Lin

Wen-Yi Hsieh

Bo-Yu Lai

Po-Yu Lin

I-Hsieh Wong

Yu-Ru Yang

Hsien-Chin Lin

Yung Feng Chang

Wen-Kai Lin

Ming-Lung Cheng

Chen-Yu Chen

Fan-Yi Hsu

Pin-Ju Liang

Jenn-Tarng Lin

Wen-Yun Wang

Ying-Yan Chen

Yuan-Tung Dai

Tzu-Hua Chiu

Kao-Ting Lai

Szu-Ping Lee

Yong-fen Hsieh

Guan-Wei Huang

Po-Wei Liang

Chen-Hsuan Liao

Szu-Wei Tseng

Po-Shao Lin

Pei-Ling Kao

Ya-Jou Hsieh

Chloe Hsin-yi Chen

David Hsu-Wei Lwu

Shyue-Shyn Lin

Win-Yi Hsieh

Hsin-Yuan Huang

Yen-Lian Lai

Tang Ming Lee

Ji-Xuan Yang

Jheng-Wei Lin

Hung Yu Lai

A semiconductor structure includes a fin extending from a substrate and oriented lengthwise in a first direction, where the fin includes a stack of semiconductor layers, an isolation feature disposed over the substrate and oriented lengthwise in a second direction perpendicular to the first direction, where the isolation feature is disposed adjacent to the fin, and a metal gate structure having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers. Furthermore, a sidewall of the bottom portion of the metal gate structure is defined by a sidewall of the isolation feature, and the top portion of the metal gate structure laterally extends over a top surface of the isolation feature.

Multi-gate field-effect transistors and methods of forming the same

A memory structure includes a first pull-up (PU) transistor and a first pull-down (PD) transistor sharing a first gate structure extending in a first direction, and a second PU transistor and a second PD transistor sharing a second gate structure extending in the first direction. The first gate structure has a first PU portion that corresponds with the first PU transistor and a first PD portion that corresponds with the first PD transistor. The second gate structure has a second PU portion that corresponds with the second PU transistor and a second PD portion that corresponds with the second PD transistor. The first and second PU portion each has a first dimension in a second direction perpendicular to the first direction, and the first and second PD portion each has a second dimension in the second direction. The first dimension is greater than the second dimension.

Memory structure and method for manufacturing the same

A device a includes a substrate, two source/drain (S/D) features over the substrate, and semiconductor layers suspended over the substrate and connecting the two S/D features. The device further includes a dielectric layer disposed between two adjacent layers of the semiconductor layers and an air gap between the dielectric layer and one of the S/D features, where a ratio between a length of the air gap to a thickness of the first dielectric layer is in a range of 0.1 to 1.0.

Method and structure for air gap inner spacer in gate-all-around devices

A method includes providing a semiconductor substrate having a first region and a second region, epitaxially growing a semiconductor layer above the semiconductor substrate, patterning the semiconductor layer to form a first fin in the first region and a second fin in the second region, and depositing a dielectric material layer on sidewalls of the first and second fins. The method also includes performing an anneal process in driving dopants into the dielectric material layer, such that a dopant concentration in the dielectric material layer in the first region is higher than that in the second region, and performing an etching process to recess the dielectric material layer, thereby exposing the sidewalls of the first and second fins. A top surface of the recessed dielectric material layer in the first region is lower than that in the second region.

Multi-gate transistor channel height adjustment

In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.

Method of manufacturing a semiconductor device and a semiconductor device

Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.

Dielectric isolation structure for multi-gate transistors

An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is on a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is on a backside of the source epitaxial structure and a backside of the drain epitaxial structure and has an air gap therein. The backside via extends through the backside dielectric layer to a first one of the source epitaxial structure and the drain epitaxial structure.

Integrated circuit structure with backside dielectric layer having air gap

Semiconductor devices including backside vias with enlarged backside portions and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; a first dielectric layer on a backside of the first device layer; a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a backside interconnect structure on a backside of the first dielectric layer and the first contact, the first contact including a first portion having first tapered sidewalls and a second portion having second tapered sidewalls, widths of the first tapered sidewalls narrowing in a direction towards the backside interconnect structure, and widths of the second tapered sidewalls widening in a direction towards the backside interconnect structure.

Semiconductor devices including backside vias and methods of forming the same

A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers connected to the source/drain feature, a gate structure between adjacent channel layers and wrapping the channel layers, and an inner spacer between the source/drain feature and the gate structure and between adjacent channel layers. The source/drain feature has a first interface with a first channel layer of the channel layer. The first interface has a convex profile protruding towards the first channel layer.

Devices with improved operational current and reduced leakage current

A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Methods of forming of inner spacer structure using semiconductor material with variable germanium concentration

The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Multigate device structure with engineered cladding and method making the same

A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

Methods for forming source/drain features

A semiconductor device according to the present disclosure includes a dielectric fin having a helmet layer, a gate structure disposed over a first portion of the helmet layer and extending along a direction, and a dielectric layer adjacent the gate structure and disposed over a second portion of the helmet layer. A width of the first portion along the direction is greater than a width of the second portion along the direction.

Dielectric fin structure

A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.

Gate all around device and method of forming the same

Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes a circuit region and a seal ring region surrounding the circuit region. The seal ring region includes a first active region extending lengthwise in a first direction and a first gate structure disposed on the first active region. The first gate structure extends lengthwise in a second direction that is tilted from the first direction. The first direction and the second direction form a tilted angle therebetween.

Seal ring structures

Growing community of inventors

Hsinchu, Taiwan

Yuan-Ching Peng