Mediatek Corporation

Mediatek Incorporation

Nephos (Hefei) Co. Ltd.

Yuan-Chin Liu

Tzu-Hung Lin

Yi-Hung Chen

Chang-Po Ma

Tse-Hsiang Hsu

Wen-Yi Wu

Chih-Cheng Chen

Chih-Ching Yu

Ming-Yang Chao

Chih-Hsiung Chu

Che Yuan Jao

A semiconductor package structure is provided. The semiconductor package structure includes a first substrate having a first wiring structure; and a second substrate having a second wiring structure, wherein the first substrate and the second substrate are arranged side-by-side, and the first substrate and the second substrate are surrounded and separated by a molding material. The semiconductor package structure also includes a redistribution layer disposed over the first substrate and the second substrate, wherein the redistribution layer is electrically coupled to the first wiring structure and the second wiring structure; and a frame surrounding the first substrate and the second substrate.

Semiconductor package structure

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a first semiconductor die, and a second semiconductor die. The substrate includes a first substrate partition and a second substrate partition. The first substrate partition has a first wiring structure. The second substrate partition is adjacent to the first substrate partition and has a second wiring structure. The first substrate partition and the second substrate partition are surrounded by a first molding material. The first semiconductor die is disposed over the substrate and electrically coupled to the first wiring structure. The second semiconductor die is disposed over the substrate and electrically coupled to the second wiring structure.

A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method

A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

Wafer-level package having one die with its clock source shared by multiple dies and associated clock generating method

A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method

A write strategy setting apparatus applied in an optical disc drive includes a storage unit, an error calculator, and a write strategy controller. The storage unit stores an initial write strategy including a plurality of write strategy parameter sets corresponding to a plurality of data set types; the error calculator calculates an error value set for each data set type generated by the optical disc drive utilizing a corresponding write strategy parameter set in the initial write strategy, and stores the calculated error value set into the storage unit to thereby overwrite the write strategy parameter set; and the write strategy controller determines a modified write strategy by referring to a plurality of error value sets stored in the storage unit and the initial write strategy, and then storing the modified write strategy into the storage unit.

Write strategy setting apparatus utilizing shared storage unit and method thereof

A delay circuit comprising a delay measurement unit, a delay mapping unit and a map delay module. The delay measurement unit generates a mapping table according to a reference signal and a reference clock signal. The delay mapping unit generates a mapped delay selection signal according to an input selection signal and at least a mapping value from the mapping table. The map delay module delays an input data signal to generate an output data signal according to the mapped delay selection signal.

Delay circuit and related method thereof

An apparatus for writing data to an optical storage media and a servo control unit and a laser diode driver unit thereof. The apparatus making a laser diode emit light includes a servo control unit and a laser diode driver unit. The servo control unit includes a control unit for controlling a burning procedure and a modulation unit for outputting an encoded signal. The laser diode driver unit receives the encoded signal and includes a PLL unit, a write strategy generation unit and a lock/unlock detection unit. The PLL unit outputs at least one of a second clock signal and a second data signal according to the encoded signal. The write strategy generation unit outputs a control signal to control the laser diode according to the second clock signal and the second data signal. The lock/unlock detection unit outputs a lock indicator or an unlock indicator to the control unit.

Apparatus for writing a data to an optical storage media and servo control unit and laser diode driver unit thereof

Level shifters capable of setting logic level of the output signals thereof to a pre-defined known state during power-up are provided, in which a first logic unit is powered by a first power voltage, receives input signals with a core power voltage and comprises first and second output terminals. First and second drivers are coupled between the first output terminal and the first power voltage and between the second output terminal and the second power voltage respectively. When one of the first and second power voltages is not ready during power-up, the first driver matches a voltage level on the first output terminal with the first power voltage by AC coupling and the second driver pulls low or maintains a voltage level on the second output terminal.

Level shifters

A delay circuit includes a first delay module, a delay measurement unit and a fault judge unit. The first delay module has a first delay circuit with at least one delay stage. The delay measurement unit is used for measuring a first delay amount and a second delay amount of the first delay chain respectively corresponding to a first number and a second number of delay stages. The fault judge unit is used for determining if the first delay chain has delay faults or not according to the first and second delay amounts.

Delay circuit and related method

A method for tuning a plurality of write strategy parameters of an optical storage device includes detecting a plurality of lengths, each length corresponding to a pit or a land on an optical storage medium accessed by the optical storage device, performing calculations corresponding to a plurality of data set types and generating a plurality of data-to-clock edge deviations respectively corresponding to the data set types, and utilizing the data-to-clock edge deviations for tuning the write strategy parameters corresponding to the data set types respectively.

Methods for tuning write strategy parameters utilizing data-to-clock edge deviations, and systems thereof

In a method and apparatus for generating optimum write power, a control unit controls a write voltage generating unit to generate sequentially write voltages of different levels to drive an optical read/write head to generate different write powers so as to write data on a plurality of write intervals of an optical recording medium in sequence. Simultaneously, a detecting and computing circuit detects a peak value, a first level and a second level of a write reflected signal generated by each write interval for computation so as to obtain a first control parameter of each write interval, and detects a peak value, a bottom value and a direct current level of a read reflected signal generated during reading of each write interval for computation so as to obtain a second control parameter of each write interval, thereby generating an optimum write power based on optimal first and second control parameters.

Method for generating control parameters for optimum write power and apparatus therefor

A write signal control circuit in an optical disk drive for adjusting the duty cycle of the write signals by a duty cycle adjusting unit. The write signal control circuit includes a write signal generator for converting an EFM signal into the write signals according to the write strategy waveform generating rules, a duty cycle adjusting unit for adjusting the duty cycle of each write signal according to adjusting parameters and for outputting adjusted write signals, and a duty cycle detector for detecting the duty cycle of each adjusted write signal and outputting a respective duty cycle control signal. The duty cycle adjusting unit further receives the duty cycle control signal to adapt the adjusting parameters.

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Hsinchu, Taiwan

Yuan-Chin Liu