Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Yun Peng

Keng-Chu Lin

Fu-Ting Yen

Chung-Chi Ko

Mrunal Abhijith Khaderbad

Joung-Wei Liou

Tze-Liang Lee

Jung-Hau Shiu

Shuen-Shin Liang

Sung-Li Wang

Chia-Hung Chu

Tsu-Hsiu Perng

Wen-Kuo Hsieh

Hui-Chun Yang

Ting-Ting Chen

Guan-Yao Tu

De-Yang Chiou

Wei-Ting Yeh

Po-Cheng Shih

Hung-Yi Huang

Chen-Han Wang

Chia Cheng Chou

Khaderbad Mrunal Abhijith

Kuei-Lin Chan

Zheng-Yong Liang

Yin-Jie Pan

Shing-Chyang Pan

Fang-Wei Lee

Yasutoshi Okuno

Kuang-Yuan Hsu

Shih-Cheng Chen

Hsu-Kai Chang

Chen-Hao Wu

Jei-Ming Chen

Han-De Chen

Kenichi Sano

Chun-Hao Hsu

Huang-Lin Chao

Chia-I Shen

Yu-Wei Lu

Cheng-I Chu

Ko-Feng Chen

Sung-li Wang

Chih-Yuan Yao

Yi-Rui Chen

Tsu-hsiu Perng

Chen-han Wang

Chia-Yun Cheng

Zheng Yong Liang

Cheng-Hsiung Liu

An-Di Sheu

I-Wen Hsu

Provided is a dielectric material composition and related methods. The method includes patterning a substrate to include a first feature, a second feature adjacent to the first feature, and a trench disposed between the first and second features. The method further includes depositing a dielectric material over the first feature and within the trench. In some embodiments, the depositing the dielectric material includes flowing a first precursor, a second precursor, and a reactant gas into a process chamber. Further, while flowing the first precursor, the second precursor, and the reactant gas into the process chamber, a plasma is formed within the process chamber to deposit the dielectric material.

Dielectric material and methods of forming same

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate formed with a semiconductor device so as to cover the semiconductor device, wherein the first bonding layer includes a first metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, wherein the second bonding layer includes a second metal oxide material in an amorphous state; conducting a surface modification process on the first bonding layer and the second bonding layer; bonding the device substrate and the carrier substrate to each other through the first and second bonding layers; and annealing the first and second bonding layers so as to convert the first and second metal oxide materials from the amorphous state to a crystalline state.

Wafer bonding method and semiconductor structure obtained by the same

A method for manufacturing a semiconductor structure includes: forming a first bonding layer on a device substrate, the first bonding layer including a first bonding sub-layer and a second bonding sub-layer, the first bonding sub-layer including a first metal oxide material in an amorphous state and a plurality of metal nanoparticles, the second bonding sub-layer including a second metal oxide material in an amorphous state; forming a second bonding layer on a carrier substrate, the second bonding layer including a third metal oxide material in an amorphous state; conducting a surface modification process on the first and second bonding layers; bonding the device and carrier substrates to each other through the first and second bonding layers; and annealing the first and second bonding layers to convert the first, second, and third metal oxide materials from the amorphous state to a crystalline state.

Metal nanoparticles in an amorphous bonding layer between a device substrate and carrier substrate

A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

Seam-top seal for dielectrics

A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate forming a superlattice structure with first and second nanostructured layers on the fin structure, forming a source/drain (S/D) opening in the superlattice structure, forming an isolation opening in the fin structure and below the S/D opening, forming a first isolation layer in the isolation opening, selectively forming an oxide layer on sidewalls of the S/D opening, selectively forming an inhibitor layer on the oxide layer, selectively depositing a second isolation layer on the first isolation layer, and forming S/D regions in the S/D opening on the second isolation layer.

Isolation structures in semiconductor devices

The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

Debonding structures for wafer bonding

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Method and structure for barrier-less plug

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Inner spacers for gate-all-around semiconductor devices

The present disclosure describes a semiconductor structure having bonded wafers with storage layers and a method to bond wafers with storage layers. The semiconductor structure includes a first wafer including a first storage layer with carbon, a second wafer including a second storage layer with carbon, and a bonding layer interposed between the first and second wafers and in contact with the first and second storage layers.

Storage layers for wafer bonding

The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

Interconnect structure and method for manufacturing the interconnect structure

A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.

Inner spacer for semiconductor device

The present disclosure is directed to method for the fabrication of spacer structures between source/drain epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form spacer cavities, and depositing a spacer layer on the fin structure to fill the spacer cavities. Further, treating the spacer layer with a microwave-generated plasma to form an oxygen concentration gradient within the spacer layer outside the spacer cavities and removing, with an etching process, the treated portion of the spacer layer. During the etching process, a removal rate of the etching process for the treated portion of the spacer layer is based on an oxygen concentration within the oxygen concentration gradient.

Inner spacer structures for gate-all-around field effect transistors

The present disclosure describes a semiconductor device that includes a transistor. The transistor includes a source/drain region that includes a front surface and a back surface opposite to the front surface. The transistor includes a salicide region on the back surface and a channel region in contact with the source/drain region. The channel region has a front surface co-planar with the front surface of the source/drain region. The transistor further includes a gate structure disposed on a front surface of the channel region. The semiconductor device also includes a backside contact structure that includes a conductive contact in contact with the salicide region and a liner layer surrounding the conductive contact.

Liner layer for backside contacts of semiconductor devices

A device includes a semiconductive substrate, a fin structure, and an isolation material. The fin structure extends from the semiconductive substrate. The isolation material is over the semiconductive substrate and adjacent to the fin structure, wherein the isolation material includes a first metal element, a second metal element, and oxide.

Device of dielectric layer

Growing community of inventors

Hsinchu, Taiwan

Yu-Yun Peng