Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Yu-Wei Zhang

Shih-Yen Lin

Si-Chen Lee

Kuan-Chao Chen

Po-Cheng Tsai

Chi Chen

A method includes forming an interlayer dielectric (ILD) layer over a transistor; forming a first inter-metal dielectric (IMD) layer over the ILD layer; etching a via opening extending through the first IMD layer; forming a first 2-D material layer lining along sides and a bottom of the via opening; depositing a first metal in the via opening and over the first 2-D material layer; performing a chemical mechanism polishing (CMP) process to the first metal until the first IMD layer is exposed; forming a second IMD layer over the first IMD layer; etching a trench in the second IMD layer; forming a second 2-D material layer lining along sides and a bottom of the trench; and depositing a second metal over the second 2-D material layer at a temperature lower than a temperature of depositing the first metal over the first 2-D material layer.

Integrated circuit structure and method for forming the same

A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

Method for forming 2-D material semiconductor device with improved source/drain electrodes and gate dielectric

Growing community of inventors

Hualien County, Taiwan

Yu-Wei Zhang