Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Tse Lai

Shih-Ming Chang

Ya Hui Chang

Ya-Hui Chang

Ken-Hsien Hsieh

Chun-Yen Chang

Chih-Kai Yang

Yu-Tien Shen

Minfeng Chen

Sheng-Min Wang

Hsiang-Ming Chang

Manuel Alejandro Fernandez Lopez

Hsin-Chih Wang

Yu-Fu Wang

In a method of manufacturing a semiconductor device, a conductive pattern is formed in a surface region of a dielectric layer, a mask pattern including an opening over the conductive pattern is formed over the dielectric layer, a part of the conductive pattern is converted into a high-resistant part having a higher resistivity than the conductive pattern before the converting through the opening, and the mask pattern is removed.

Method of manufacturing semiconductor devices and semiconductor devices

A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

Critical dimension uniformity (CDU) control method and semiconductor substrate processing system

Methods of forming self-aligned vias and devices having self-aligned vias are provided. In some embodiments, a method includes forming a first via on a conductive layer. A mask is formed over the conductive layer, and the mask has an opening overlying a portion of the conductive layer and at least partially overlying the first via. A first line end of the conductive layer is formed by selectively removing the portion of the conductive layer, with the first via being aligned with the first line end of the conductive layer.

Self-aligned cut-metal layer method

A first bright field reticle and a second bright field reticle are utilized for a double exposure EUV photolithography process in which exposure areas of the first and second bright field reticles overlap. The first and second reticles each include, respectively, a substrate, a reflective multilayer on the substrate, a main pattern of absorption material on the reflective multilayer, a black border area, and an additional absorption area of the absorption material between the black border and the main pattern.

Method and system to introduce bright field imaging at stitching area of high-NA EUV exposure

A method of manufacturing a semiconductor device includes forming a first resist layer over a substrate, and forming a second resist layer over the first resist layer. The second resist layer is patterned to expose a portion of the first resist layer to form a second resist layer pattern. The first resist layer is exposed to extreme ultraviolet (XUV) radiation diffracted by the second resist layer pattern. Portions of the first resist layer exposed to the XUV radiation diffracted by the second resist layer are removed.

Method of manufacturing a semiconductor device

In a method of manufacturing a semiconductor device, a first conductive layer is formed over a first interlayer dielectric (ILD) layer disposed over a substrate, a second ILD layer is formed over the first conductive layer, a via is formed in the second ILD layer to contact an upper surface of the first conductive layer, a hard mask pattern is formed over the second ILD layer, the second ILD layer and the first conductive layer are patterned by using the hard mask pattern as an etching mask, thereby forming patterned second ILD layers and first wiring patterns, after the patterning, the hard mask pattern is removed, and a third ILD layer is formed between the patterned second ILD layers and the first wiring patterns.

Method of manufacturing a via and a metal wiring for a semiconductor device

A structure includes a dielectric layer, and a metal line in the dielectric layer. The metal line has a first straight edge and a second straight edge extending in a lengthwise direction of the metal line. The first straight edge and the second straight edge are parallel to each other. A via is underlying and joined to the metal line. The via has a third straight edge underlying and vertically aligned to the first straight edge, and a first curved edge and a second curved edge connecting to opposite ends of the third straight edge.

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Zhubei, Taiwan

Yu-Tse Lai