Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

National Taiwan University

Yu-Ting Yen

Kei-Wei Chen

Chih Hung Chen

William Weilun Hong

Cheng-Yu Kuo

Te-Chien Hou

Ying-Ho Chen

Chi-Ming Tsai

Hui-Chi Huang

Kao-Feng Liao

Teng-Chun Tsai

Wen-Kuei Liu

Yu-Chung Su

Hsuen-Li Chen

Yean-San Long

Chen-Chieh Yu

En-Yun Wang

Ren-Chin Shr

Hsiang-Ying Cheng

Sin-Yi Chou

A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

CMP system and method of use

A method includes performing Chemical Mechanical Polish (CMP) on a wafer, placing the wafer on a chuck, performing a post-CMP cleaning on the wafer, and determining cleanness of the wafer when the wafer is located on the chuck.

Detecting the cleanness of wafer after post-CMP cleaning

A defect inspection method and a defect inspection system for a solar cell are proposed, where the method includes the following steps. Output voltages and output currents of the solar cell are measured by a measuring device. A stepwise current-voltage curve (stepwise IV curve) and a fitted current-voltage curve (fitted IV curve) are generated by a processing device according to the output voltages and the output currents, and whether a first error of the fitted IV curve is less than a first error tolerance is determined by the processing device. When the first error is not less than the first error tolerance, whether there exists at least one surge in steps of the stepwise IV curve is determined by the processing device so as to determine whether the solar cell has a defect. Next, a determined result of the processing device is outputted by the output device.

Defect inspection method and system for solar cell

A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.

Planarization method, method for manufacturing semiconductor structure, and semiconductor structure

In a Surface-Enhanced Raman Scattering (SERS) substrate and the manufacturing method thereof, the SERS substrate includes a low thermal conductivity base and a plurality of metal nanoparticles (NPs). The surface of the low thermal conductivity substrate has a first surface, and the first surface has a plurality of ripple micro/nano structures. The plurality of metal NPs are non-continuously densely arranged on the ripple micro/nano structures of the first surface. The metal NPs have a height difference along the ripple micro/nano structures, and form a 3D electric field enhanced region. The manufacturing methods includes sputtering a metal nano-thin film on a surface of a low thermal conductivity base, and the surface of the low thermal conductivity base has a plurality of ripple micro/nano structures; using laser to ablate the metal nano-thin film; and forming a plurality of metal NPs, which are non-continuously densely arranged.

Surface-enhanced raman scattering substrate and manufacturing method thereof

The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.

Wafer cleaning module

An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

CMP-friendly coatings for planar recessing or removing of variable-height layers

Growing community of inventors

Kaohsiung, Taiwan

Yu-Ting Yen