Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Sheng Wang

Chi-Cheng Hung

Ching-Hwanq Su

Kei-Wei Chen

Chia-Ching Lee

Yu-Ting Lin

Ying-Lang Wang

Liang-Yueh Ou Yang

Shiu-Ko JangJian

Chung-Chiang Wu

Jung-Chih Tsao

Da-Yuan Lee

Chen-Yuan Kao

Ming-Ching Chung

Yi-Wei Chiu

Ming-Hsing Tsai

Yueh-Ching Pai

Jun-Nan Nian

Hsien-Ming Lee

Kuan-Ting Liu

Chia-Yang Wu

Ya-Wen Chiu

Chih-Hsiang Fan

Kun-Wa Kuok

Kai-Cyuan Yang

Shih-Chieh Chang

Chi-Cherng Jeng

Hsin-Yi Lee

Huai-Tei Yang

Szu-An Wu

Hung-Hsu Chen

Shih-Ho Lin

Chien-Chung Chen

Wen-Hsi Lee

Chia-Han Lai

Yu-Ren Peng

Ching-Yao Sun

Jyun-Ru Wu

Ting-Siang Su

Ren-Hau Yu

Tain-Shang Chang

Weng-Cheng Chen

Hao-Han Wei

Ying-Jing Lu

En-Ting Lee

Kun-El Chen

Wei-Yu Chen

Jyh-Cherng Sheu

Yu-Ku Lin

Wei-Ming You

Chun-I Tsai

Rueijer Lin

Yi-Ying Liu

Hung-Chang Hsu

Chun-Wen Nieh

Chih-Cherng Jeng

I-Li Chen

Pohan Kung

Hsiao-Ping Liu

Cheng-Jung Sung

Hong-Ming Wu

Hung Pin Lu

Pei-Wen Wu

Yuan Wen Lin

Pei-Shan Chang

A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

FinFET structures and methods of forming the same

A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

Low resistant contact method and structure

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Methods for forming contact plugs with reduced corrosion

In some implementations, one or more semiconductor processing tools may deposit cobalt material within a cavity of the semiconductor device. The one or more semiconductor processing tools may polish an upper surface of the cobalt material. The one or more semiconductor processing tools may perform a hydrogen soak on the semiconductor device. The one or more semiconductor processing tools may deposit tungsten material onto the upper surface of the cobalt material.

Tungsten deposition on a cobalt surface

A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.

CMOS FinFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

A metal adhesion layer may be formed on a bottom and a sidewall of a trench prior to formation of a metal plug in the trench. A plasma may be used to modify the phase composition of the metal adhesion layer to increase adhesion between the metal adhesion layer and the metal plug. In particular, the plasma may cause a shift or transformation of the phase composition of the metal adhesion layer to cause the metal adhesion layer to be composed of a (111) dominant phase. The (111) dominant phase of the metal adhesion layer increases adhesion between the metal adhesion layer.

Metal adhesion layer to promote metal plug adhesion

CMOS finFET structures including work-function materials having different proportions of crystalline orientations and methods of forming the same

A semiconductor device includes a semiconductor substrate, a gate structure, a first source/drain region, a second source/drain region, first source/drain contact and a first dielectric spacer liner. The gate structure is over the semiconductor substrate. The first source/drain region and the second source/drain region are in the semiconductor substrate and respectively on opposite sides of the gate structure. The first source/drain contact is over the first source/drain region. The first dielectric spacer liner lines a sidewall of the first source/drain contact and extends into the first source/drain region.

Semiconductor device with dielectric spacer liner on source/drain contact

A semiconductor device and method of manufacturing are provided. In an embodiment a first nucleation layer is formed within an opening for a gate-last process. The first nucleation layer is treated in order to remove undesired oxygen by exposing the first nucleation layer to a precursor that reacts with the oxygen to form a gas. A second nucleation layer is then formed, and a remainder of the opening is filled with a bulk conductive material.

Semiconductor device and methods of manufacture

A method of manufacturing a semiconductor device includes: providing a substrate; forming a gate structure on the substrate; depositing a first dielectric layer over the gate structure; depositing a conductive interconnect in a trench of the first dielectric layer thereby exposing a surface of the conductive interconnect through the first dielectric layer; depositing a conductive layer over the exposed surface of the conductive interconnect; depositing a silicon-containing layer over the conductive layer and the conductive interconnect; and forming a metal silicide layer to be a silicide form of the conductive layer by reacting the conductive layer with silicon in the silicon-containing layer.

Semiconductor device and manufacturing process thereof

A method of fabricating tantalum nitride barrier layer in an ultra low threshold voltage semiconductor device is provided. The method includes forming a high-k dielectric layer over a semiconductor substrate. Subsequently, a tantalum nitride barrier layer is formed on the high-k dielectric layer. The tantalum nitride barrier layer has a Ta:N ratio between 1.2 and 3. Next, a plurality of first metal gates is formed on the tantalum nitride barrier layer. The first metal gates are patterned, and then a second metal gate is formed on the tantalum nitride barrier layer.

Method of fabricating tantalum nitride barrier layer and semiconductor device thereof

Growing community of inventors

Tainan, Taiwan

Yu-Sheng Wang