Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

E Ink Holdings Inc.

Accton Technology Corporation

Hannstar Display Corporation

Asia Optical Co., Ltd.

Win Coat Corporation

Yu-Sheng Lin

Shin-Puu Jeng

Po-Yao Lin

Shu-Shen Yeh

Chin-Hua Wang

Ming-Chih Yew

Po-Chen Lai

Che-Chia Yang

Pei-Kuei Tsung

Yao-Sheng Wang

Chien-Hung Chen

Ted-Hong Shinn

Chih-Wen Goo

Chi-Ming Wu

Chih-Wei Chen

Chia-Kuei Hsu

Han-Hsiang Huang

Jyun-Lin Wu

Chien-Sheng Chen

Wen-Chih Chiou

Chien-Hung Zordius Chen

Yao-Chun Chuang

Shih-Chin Lin

Chen-Yu Tsai

Yuan-Chih Tsai

Ying-Chieh Chen

Wai Mun Wong

Cheng-Lung Jen

Chao-Min Chang

Tsung-Shang Wei

Shih-Che Chen

Chiani Lu

Chin-Fu Kao

Yi-Ching Wang

Yi-Ting Chen

Wen-Yi Lin

Kuang-Chun Lee

Chia-Hsiang Lin

Chien-Yu Huang

Chiung-Fu Chen

Ta-Jo Liu

Tsung-Yang Hsieh

Chih-cheng Chen

Chien Hung Chen

Wan-Tien Chen

Tung-Chien Chen

Yu-Cheng Tseng

Chih-Hua Cheng

Yen-Hao Chen

Tsung-Mou Tsai

Hsin-Hsien Lee

Yun-Hsuan Chen

Kuo-Chen Huang

Kuo-Chiang Lo

Yung-Li Huang

Chien-Tung Yu

Hung-Pin Su

Chien-Shen Chen

Yu Chen Lee

Ming-En Shih

Cheng Lung Jen

Ping-Yuan Tsai

Chen-Nan Chiu

Yung-Ta Huang

Shin-Yi Hsieh

Hsiu-Feng Yeh

Chia-Ni Lu

Ping-Tai Chen

Tsung-Shian Huang

Tsu Jui Hsu

Sheng-Liang Kuo

Kathy Yan

Hsin-Min Peng

Chun Hsien Wu

Shin-Puu Zeng

C Bernard Shung

Huang Tsung-Shian

Jen Cheng Lung

Wan-Ten Chen

Jih-Hsin Chiang

Nan-Cheng Huang

Hung-Hsing Lin

A first integrated circuit (IC) die includes a first substrate. A second IC die includes a second substrate. At least one of the first substrate or the second substrate has a first surface orientation. The first IC die is spaced apart from the second IC die. A third die electrically interconnects the first IC die to the second IC die. The third die includes a third substrate having a second surface orientation. The second surface orientation is different from the first surface orientation.

Bridge die having different surface orientation than IC dies interconnected by the bridge die

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.

Chip package structure with lid

Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.

Package structure with buffer layer embedded in lid layer

Semiconductor packages and methods of fabricating semiconductor packages include a package substrate having a recess formed in a surface of the package substrate and at least one channel in a bottom surface of the recess. The recess may be configured to accommodate a semiconductor device located over a surface of an interposer that is bonded to the package substrate. Accordingly, a minimum gap distance may be maintained between the semiconductor device and the package substrate, which may ensure that sufficient underfill material may flow between the semiconductor device and the package substrate and within the at least one channel, thereby improving of the structural coupling between the interposer and the package substrate, and reducing the likelihood of package defects, such as delamination, cracking, and/or popcorn defects.

Semiconductor package with substrate recess and methods for forming the same

A manufacturing method of a semiconductor package includes the following steps. A first semiconductor device is provided over a substrate, wherein the first semiconductor device is offset toward an edge of the substrate. A ring structure is attached to the substrate by a first adhesive layer, wherein the ring structure surrounds the first semiconductor device and comprises an overhang portion cantilevered over the edge of the substrate. A lid structure is attached to the ring structure by a second adhesive layer, wherein the lid structure covers the first semiconductor device and comprises an extending portion covering the overhang portion.

Manufacturing method of semiconductor package

In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

Package and method for forming the same

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

Chip package structure with ring dam

A semiconductor structure includes a semiconductor die containing an array of first bonding structures. Each of the first bonding structures includes a first metal pad located within a dielectric material layer and a basin-shaped underbump metallization (UBM) pad located within a respective opening in a passivation dielectric layer and contacting the first metal pad. An interposer includes an array of second bonding structures, wherein each of the second bonding structures includes an underbump metallization (UBM) pillar having a respective cylindrical shape. The semiconductor die is bonded to the interposer through an array of solder material portions that are bonded to a respective one of the first-type bonding structures and to a respective one of the second-type bonding structures.

Basin-shaped underbump plates and methods of forming the same

A semiconductor structure includes an interposer having a first planar surface, a set of non-horizontal surfaces having a top periphery that are adjoined to a periphery of the first planar surface, and a frame-shaped surface adjoined to a bottom periphery of the set of non-horizontal surfaces, sidewalls adjoined to the frame-shaped surface, and a second planar surface adjoined to the sidewalls; at least one semiconductor die attached to the interposer through a respective array of solder material portions; and an underfill material portion located between the interposer and the at least one semiconductor die and contacting a portion of the first planar surface.

Interposer including stepped surfaces and methods of forming the same

A package assembly includes a package substrate, a solder resist layer on the package substrate and including an elongated solder resist opening, and an interposer module on the package substrate and including a corner located on the elongated solder resist opening.

Package assembly including package substrate with elongated solder resist opening and methods for forming the same

A semiconductor die package is provided, including a package substrate, and two semiconductor dies disposed over the package substrate and arranged in a first direction. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. The ring structure includes a first part having a first height and a second part recessed from the bottom surface and having a second height lower than the first height. The first part includes multiple higher parts arranged side by side in at least some of side areas of the ring structure, and the second part includes multiple lower parts between the higher parts. The lower parts include multiple first lower parts arranged in multiple corner areas of the ring structure and multiple second lower parts arranged in opposite side areas of the ring structure extending in the first direction.

Semiconductor die package with ring structure

A semiconductor package includes a substrate and at least one integrated circuit (IC) die. Substrate solder resist has substrate solder resist openings exposing substrate bonding pads of the bonding surface of the substrate, and die solder resist has aligned die solder resist openings exposing die bonding pads of the bonding surface of the IC die. A ball grid array (BGA) electrically connects the die bonding pads with substrate bonding pads via the die solder resist openings and the substrate solder resist openings. The die solder resist openings include a subset A of the die solder resist openings in a region A of the bonding surface of the IC die and a subset B of the die solder resist openings in a region B of the bonding surface of the IC die. The die solder resist openings of subset A are larger than those of subset B.

Semiconductor package with ball grid array connection having improved reliability

A thermal module may include a cold plate including a cold plate base having a cold plate base protruding portion, and a cold plate cover on the cold plate base, and a heat pipe between the cold plate base and the cold plate cover, and including an upper heat pipe portion and a lower heat pipe portion in the cold plate base protruding portion.

Thermal module for a semiconductor package and methods of forming the same

A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.

Semiconductor package

A semiconductor package includes a package substrate; semiconductor devices disposed on the package substrate; a package ring disposed on a perimeter of package substrate surrounding the semiconductor devices; a cover disposed over the package ring and the semiconductor devices; a cover adhesive bonding the cover to the package ring; and a stress-reduction structure including first channels formed in an upper surface of the package ring and second channels formed in a lower surface of a portion of the cover that overlaps with the first channels.

Semiconductor package including stress-reduction structures and methods of forming the same

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Hsinchu, Taiwan

Yu-Sheng Lin