Chipmos Technologies Inc.

Chipmos Technologies (bermuda) Ltd

Holtek Semiconductor Corp.

Yu-Ren Chen

Geng-Shin Shen

Chun-Ying Lin

I-Hsin Mao

Ya-Chi Chen

Chun-Yao Liao

Tz-Cheng Chiu

Hung Tsun Lin

Yeong-Jyh Lin

Chun-Yao Laio

A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.

Packaging method involving rearrangement of dice

A chip package includes a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Chip package

A dice rearrangement package structure is provided, which a dice having an active surface and a bottom surface, and a plurality of pads is disposed on the active surface; a package body is provided to cover the dices and the plurality of pads being exposed; one ends of plurality of metal traces is electrically connected to the each pads; a protection layer is provided to cover the active surface and the other ends of the exposed metal traces is electrically connected to the plurality of conductive elements, the characteristic in that the package body is a B-stage material.

Dice rearrangement package structure using layout process to form a compliant configuration

A multi-chips stacked package method which includes providing a lead frame includes a top surface and a reverse surface formed by a plurality of inner leads and a plurality of outer leads; fixing a first chip on the reverse surface of the lead frame and the active surface of the first chip includes a plurality of first pads closed to the central region; forming a plurality of first metal wires, and the first pads are electrically connected to the first inner leads and the second inner leads by the first metal wires; forming a plurality of metal spacers on the thermal fin of the lead frame; fixing a second chip to electrically connect to the top surface of the first inner leads and the second inner leads; forming a plurality of second metal wires, and the second pads are electrically connected to the top surface of the first inner leads and the second inner leads; and flowing a molding to form an encapsulated material to cover the first chip, the first metal wires, the second chip, the second metal wires, the first inner leads and the second inner leads and the outer leads being exposed.

Method for fabricating multi-chip stacked package

A chip package structure includes a chip-placed frame that having an adhesive layer thereon; a chip includes a plurality of pads on an active surface thereon, and is provided on the adhesive layer; a package structure is covered around the four sides of the chip-placed frame, and the height of the package structure is larger than the height of the chips; a plurality of patterned metal traces is electrically connected to the plurality of pads, another end is extended out to cover the surface of the package structure; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is exposed; a plurality of patterned UBM layer is formed on the extended surface of the patterned metal traces; and a plurality of conductive elements is formed on the patterned UBM layer and is electrically connected to one end of the exposed portion of the patterned metal traces.

Chip package structure and the method thereof with adhering the chips to a frame and forming UBM layers

The invention mainly relates to a power on reset signal generating circuit and method thereof wherein said reset signal remains as a constant being independent of rising or descending power or repeated switching. The power on reset signal circuit can be implemented by a conventional RC power on reset circuit together with a coupled N-type transistor switch to charge or discharge the capacitor inside the conventional RC power on reset circuit.

Power on reset generating circuit and method thereof

A die-stacked package structure, wherein a plurality of dies are stacked on the substrate with a rotation so that a plurality of metallic ends and the metal pad on each die on the substrate can all be exposed; a plurality of metal wires are provided for electrically connecting the plurality of metal pads on the plurality of dies with the plurality metallic ends on the substrate in one wire bonding process; then an encapsulate is provided for covering the plurality of stacked dies, a plurality of metal wires and the plurality of metallic ends on the substrate.

Zigzag-stacked package structure

A fuse option circuit including a fuse, a control switch, a latch, and a logical operational controller is provided. The latch stores a selected level. The logical operational controller outputs a selected result signal and feedbacks a control signal to the control switch. The level of the control signal determines whether the control switch is on or off. Therefore, the required level is input to the latch and the working mode having an ultra low current is selected. Furthermore, when the fuse is in an untrimmed state, the level of the selected result signal could be selected by a reset pulse signal of the latch in order to test a product. Afterward, it is determined whether the fuse is trimmed or not. When the fuse is in a trimmed state, the level of the selected result signal is established by a rising edge of the reset pulse signal.

Fuse option circuit

A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Stacked chip packaging with heat sink structure

A chip package including a thermal enhanced plate, contacts around the thermal enhanced plate and electrically insulated from the thermal enhanced plate, a film-like circuit layer disposed on the contacts and the thermal enhanced plate, a conductive adhesive layer, a first molding, and at least one chip disposed on the film-like circuit layer is provided. The conductive adhesive layer is disposed between the contacts and the film-like circuit layer electrically connected to the contacts through the conductive adhesive layer. The chip has a back surface, an active surface and many bumps disposed thereon, and the chip is electrically connected to the film-like circuit layer via the bumps. The first molding at least encapsulates a portion of the thermal enhanced plate, the conductive adhesive layer, parts of the contacts and at least a portion of the film-like circuit layer. Therefore, heat dissipation efficiency of the light emitting chip package is improved.

Manufacturing method of chip package

A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.

Chip package structure and fabricating method thereof

Disclosed is an improved circuit and method for generating a power on reset signal, the circuit being a two-stage circuit comprising a delay-stage circuit and an output-stage circuit. The delay-stage circuit delays a time for a power on reset signal generated in the output-stage circuit changing from low to high, so that a power voltage having a low rising speed may be normally reset. Further, the two stages provide charging paths and discharging paths so that the power on reset signal may be prevented from changing from high to low when it has changed from low to high, when noises are presented on the power voltage.

Growing community of inventors

Hsinchu, Taiwan

Yu-Ren Chen