Advanced Micro Devices Corporation

Spansion Llc.

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Candescent Technologies Corporation

Fujitsu Corporation

Cypress Semiconductor Corporation

Fasl LLC

Fujitsu Amd Semiconductor Limited

Canon Kabushiki Kaisha

Yu Nan Sun

Mark T Ramsbey

Chi K Chang

Angela Tai Hui

Hiroyuki Kinoshita

Tuan Duc Pham

Sameer S Haddad

Unsoon Kim

Yider Wu

Fei Wang

Hiroyuki Ogawa

Christopher J Spindt

Yowjuang William Liu

Kuo-Tung Chang

Mark S Chang

Anthony P Schmid

David L Morris

Theodore S Fahlen

Hung-Sheng Chen

Shenqing Fang

Mark W Randolph

Jean Y Yang

Kashmir S Sahota

Richard J Huang

Vei-Han Chan

Tatsuya Kajita

Chung-You Hu

Kelwin Ko

Ramkumar Subramanian

Hidehiko Shiraiwa

Pau-Ling Chen

Binh Quang Le

Shane Charles Hollmer

Wenge Yang

Wenmei Li

YongZhong Hu

Jean Yee-Mei Yang

Shoichi Kawamura

Hideki Komori

Christopher Foster

Mike Van Buskirk

Hisayuki Shimada

Minh Van Ngo

Nian Niles Yang

Richard M Fastow

Cyrus E Tabery

Michael Allen Van Buskirk

Yue-Song He

Yi He

Donald L Wollesen

Chun Chen

Zhizheng Liu

David K Liu

Hsingya Arthur Wang

Chungho Lee

Harpreet Kaur Sachar

Weidong Qian

Kenneth W Au

John R Behnke

Tommy C Hsiao

Emmanuel H Lingunis

Keizaburo Yoshie

Tommy C Hsaio

Basab Banerjee

Calvin T Gabriel

Michael K Templeton

Jeffrey Allan Shields

Darlene G Hamilton

Timothy J Thurgate

Tazrien Kamal

Krishnashree Achuthan

Kuo Tung Chang

Amol Ramesh Joshi

Inkuk Kang

Emmanuil Lingunis

Sung-Yong Chung

Maria Chow Chan

Cinti Xiaohua Chen

Gulzar Ahmed Kathawala

Christopher H Raeder

Edward Franklin Runnion

Tim Thurgate

David H Chi

Fred Cheung

King Wai Kelwin Ko

Michael David Fliesler

David R Morris

David H Matsumoto

Ming-Sang Kwan

Kazuhiro Mizutani

Sung-Chul Lee

Fred T K Cheung

Kenneth Wo-Wai Au

Mimi Xuefeng Qian

Judith Quan Rizzuto

Kelwin King Wai Ko

Yuji Mizuguchi

Yanxia (Emma) Lin

Xianmin Yi

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming a dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different.

Charge trapping split gate embedded flash memory and associated methods

A process for forming tilted edge wordline implants is disclosed. The process includes forming a first drain implant in a substrate, forming a first tilted implant in a substrate adjacent a first edge wordline to supplement said first drain implant where the first tilted implant is provided at a tilt angle from a first direction and forming a second tilted implant in the substrate adjacent a second edge wordline to supplement another first drain implant where the second tilted implant is provided at a tilt angle from a second direction. A second drain implant is formed in the substrate.

Process for forming edge wordline implants adjacent edge wordlines

An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.

Dual storage node memory

A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the semiconductor substrate in the core region and not in the periphery region. A wordline-gate layer is formed and implanted with dopant in the core region and not in the periphery region. A wordline and gate are formed. Source/drain junctions are implanted with dopant in the semiconductor substrate around the gate, and the gate is implanted with a gate doping implantation in the periphery region and not in the core region.

Memory manufacturing process with bitline isolation

Systems, methods, and devices that facilitate applying a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected during a read or verify operation to facilitate reducing adjacent wordline disturb are presented. A memory component can comprise an optimized operation component that can apply a predefined negative gate voltage to wordlines adjacent to a selected wordline associated with a memory cell selected for a read or verify operation, based at least in part on predefined operation criteria, to facilitate reducing adjacent wordline disturb in the selected memory cell to facilitate reducing a shift in the voltage threshold and maintain a desired operation window. The optimized operation component optionally can include an evaluator component that can facilitate determining whether a negative gate voltage applied to adjacent wordlines is to be adjusted to facilitate reducing adjacent wordline disturb below a predetermined threshold amount.

Applying negative gate voltage to wordlines adjacent to wordline associated with read or verify to reduce adjacent wordline disturb

Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

Thin oxide dummy tiling as charge protection

A drain () includes a lightly-doped shallow impurity region () aligned with a control gate (), and a heavily-doped deep impurity region () aligned with a sidewall film () and doped with impurities at a concentration higher than that of the lightly-doped shallow impurity region (). The lightly-doped shallow impurity region () leads to improvement of the short-channel effect and programming efficiency. A drain contact hole forming portion () is provided to the heavily-doped impurity region () to reduce the contact resistance at the drain ().

Semiconductor memory device

A semiconductor device is disclosed and provided. The semiconductor device includes a pad metal layer having a perimeter area and a center area. Further, the semiconductor device has a lower metal layer having a plurality of apertures below the center area of the pad metal layer. Moreover, an interlayer dielectric is formed between the pad metal layer and the lower metal layer. In an embodiment, the semiconductor device also includes a plurality of vias formed in the interlayer dielectric. The vias electrically couple the pad metal layer and the lower metal layer. Additionally, the vias are located below the perimeter area of the pad metal layer.

Semiconductor device having a pad metal layer and a lower metal layer that are electrically coupled, whereas apertures are formed in the lower metal layer below a center area of the pad metal layer

A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

Shallow trench isolation approach for improved STI corner rounding

A method for performing a bit line implant is disclosed. The method includes forming a group of structures on an oxide-nitride-oxide stack of a semiconductor device. Each structure of the group of structures includes a polysilicon portion and a hard mask portion. A first structure of the group of structures is separated from a second structure of the group of structures by less than 100 nanometers. The method further includes using the first structure and the second structure to isolate a portion of the semiconductor device for the bit line implant.

Bit line implant

A method and apparatus for coupling to a common line in an array. Gate structures of an integrated circuit are formed. Source and drain regions adjacent to the gate structures are implanted. A source contact from a metal Vss line to a source region is formed. Dopants of the source and drain regions diffuse laterally to overlap. The overlapping diffusion regions conduct and couple the drain region to a source region. Beneficially, the drain region is coupled to the metal Vss line. As a beneficial result, source contacts may be formed along a line of drain contacts in associated rows of drain contacts, and coupled to a common source line via the novel overlapping diffusion regions. A plurality of word lines may be formed without any bending in the word lines to accommodate source contacts that are larger than the source line. Numerous deleterious consequences of bent word lines, for example decreased array density and detrimental electrical behavior of memory cells in the vicinity of bent word lines, may beneficially be overcome by embodiments of the present invention.

Method and apparatus for coupling to a common line in an array

A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

Methodsandare disclosed for fabricating shallow isolation trenches and structures in multi-bit SONOS flash memory devices. One method aspectcomprises forminga multi-layer dielectric-charge trapping-dielectric stackover a substrateof the wafer, for example, an ONO stack, removingthe multi-layer dielectric-charge trapping-dielectric stackin a periphery regionof the wafer, thereby defining a multi-layer dielectric-charge trapping-dielectric stackin a core regionof the wafer. The methodfurther comprises forminga gate dielectric layerover the periphery regionof the substrate, forminga first polysilicon layerover the multi-layer dielectric-charge trapping-dielectric stackin the core regionand the gate dielectricin the periphery region, then concurrently formingan isolation trenchin the substratein the core regionand in the periphery region. Thereafter, the isolation trenches are filledwith a dielectric material, and a second polysilicon layerthat is formedover the first polysilicon layerand the filled trenches, forming an self-aligned STI structure. The methodavoids ONO residual stringers at STI edges in the periphery region, reduces active region losses, reduces thinning of the periphery gate oxide and the ONO at the STI edge, and reduces dopant diffusion during isolation implantations due to reduced thermal process steps.

Self-aligned STI SONOS

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Sunnyvale, CA, United States of America

Yu Nan Sun