Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

United Microelectronics Corp.

Mediatek Corporation

Other

National Taiwan University

Primax Electronics Ltd.

National Yang Ming Chiao Tung University

National Science Council

Parabellum Strategic Opportunities Fund LLC

Chang International Enterprise Co., Ltd.

Yu-Ming Lin

Sai-Hooi Yeong

Chih-Hao Wang

Chia-Hao Chang

Han-Jong Chia

Bo-Feng Young

Jia-Chuan You

Lin-Yu Huang

Cheng-Chi Chuang

Tien-Lu Lin

Meng-Han Lin

Li-Zhen Yu

Chun-Chieh Lu

Chih-Yu Chang

Chung-Te Lin

Sheng-Chen Wang

Chao-I Wu

Chenchen Jacob Wang

Chi On Chui

Sheng-Tsung Wang

Huan-Chieh Su

Hai-Ching Chen

Chun-Yuan Chen

Mauricio Manfrini

Feng-Cheng Yang

Wai-Yi Lien

Shih-Chuan Chiu

Chun Hsiung Tsai

Clement Hsingjen Wann

Yih Wang

Cheng-Yi Peng

Kuo-Feng Yu

Yen-Chieh Huang

Shahaji B More

Wei-Hao Wu

Zhiqiang Wu

Cheng-Tung Huang

Shih-Lien Linus Lu

Zhi-Chang Lin

Yi-Ching Liu

Ken-Ichi Goto

Ziwei Fang

Jia-Ni Yu

Jia-Ming Chen

Li-Duan Tsai

Ya-Ting Chang

Carlos H Diaz

Chia-En Huang

Jean-Pierre Colinge

Ming-Hsi Yeh

Georgios Vellianitis

Yasutoshi Okuno

Sheng-Chih Lai

Kai-Hsuan Lee

Chi-On Chui

Chun-Hsiung Tsai

Meng-Hsuan Hsiao

Huai-Ying Huang

I-Ming Chang

Nuo Xu

Kuo-Cheng Chiang

Chih-Hsin Ko

Chung-Wei Hsu

Ting-Hung Hsu

Kuo-Chang Chiang

Yee-Chia Yeo

Yu-Cheng Tung

Chih-Sheng Chang

Li-Te S Lin

Ling-Yen Yeh

Ta-Pen Guo

Hsin-Yen Huang

Chung-Cheng Wu

Samuel C Pan

Marcus Johannes Henricus Van Dal

Yi-Hsun Chiu

Han-Ting Tsai

Pei-Yu Wang

Chandrashekhar Prakash Savant

Wilman Tsai

Chia-Ta Yu

Chi-Lin Teng

Su Xing

Chia-en Huang

Ting-Ya Lo

Kuo-Cheng Ching

Chih-Hao Chang

Shyh-Fann Ting

Chia-Hao Hsu

Yi-Tang Lin

Kai-Wen Cheng

Yu-Jen Chen

Tzer-Min Shen

Lei-Lung Tsai

Po-Tsun Liu

Meng-Yi Wu

Wen-Han Hung

Kun-Hsien Lee

Wei-Chih Wen

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.

Semiconductor device

A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Transistor, memory device and manufacturing method of memory device

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Semiconductor device structure

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

Provided are a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes: a gate electrode; a ferroelectric layer, disposed on the gate electrode; a channel layer, disposed on the ferroelectric layer; a pair of source/drain (S/D) electrodes, disposed on the channel layer; a first insertion layer, disposed between the gate electrode and the ferroelectric layer; and a second insertion layer, disposed between the ferroelectric layer and the channel layer, wherein the second insertion layer has a thickness less than a thickness of the first insertion layer.

Ferroelectric memory device and method of forming the same

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Thin film transistor including a compositionally- graded gate dielectric and methods for forming the same

A method for fabricating a three-dimensional memories is provided. A stack with multiple levels is formed, and each of the levels includes an isolation layer, a metal layer, and a semiconductor layer between the isolation layer and the metal layer. A first trench and a plurality of second trenches are formed along each parallel line in the stack of the levels. The isolation layers and the metal layers in the parallel lines are removed through the first trench and the second trenches, so as to expose the semiconductor layers in the parallel line. A plurality of memory cells are formed in the parallel lines of the levels. In each of the levels, each of the memory cells includes a transistor and a channel of the transistor is formed by the semiconductor layer in the parallel line.

Method for fabricating three-dimensional memory

Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.

Ferroelectric device and methods of forming the same

A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.

A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a gate, a ferroelectric layer disposed on the gate; a first channel layer disposed on the ferroelectric layer, a second channel layer disposed on the ferroelectric layer, and source and drain regions disposed on the first channel layer. The first channel layer includes a first thickness and the second channel layer includes a second thickness. A ratio of the first thickness and the second thickness is less than ⅗.

Source/drain engineering for ferroelectric field effect transistors

A device is disclosed, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the first layer. The first pass-gate transistor is coupled between a first bit line and a first terminal of the latch circuit, and the second pass-gate transistor is coupled between a second bit line and a second terminal of the latch circuit.

Integrated circuit device and manufacturing method of the same

A 3D memory array in which epitaxial source/drain regions which are horizontally merged and vertically unmerged are used as source lines and bit lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a first channel region over a semiconductor substrate; a first epitaxial region electrically coupled to the first channel region; a second epitaxial region directly over the first epitaxial region in a direction perpendicular to a major surface of the semiconductor substrate; a dielectric material between the first epitaxial region and the second epitaxial region, the second epitaxial region being isolated from the first epitaxial region by the dielectric material; a gate dielectric surrounding the first channel region; and a gate electrode surrounding the gate dielectric.

Memory array including epitaxial source lines and bit lines

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Hsinchu, Taiwan

Yu-Ming Lin