Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

United Microelectronics Corp.

Mediatek Corporation

Other

National Taiwan University

Primax Electronics Ltd.

National Yang Ming Chiao Tung University

National Science Council

Parabellum Strategic Opportunities Fund LLC

Chang International Enterprise Co., Ltd.

Yu-Ming Lin

Sai-Hooi Yeong

Chih-Hao Wang

Chia-Hao Chang

Han-Jong Chia

Bo-Feng Young

Jia-Chuan You

Lin-Yu Huang

Cheng-Chi Chuang

Tien-Lu Lin

Meng-Han Lin

Li-Zhen Yu

Chun-Chieh Lu

Chih-Yu Chang

Chung-Te Lin

Sheng-Chen Wang

Chao-I Wu

Chi On Chui

Chenchen Jacob Wang

Sheng-Tsung Wang

Hai-Ching Chen

Huan-Chieh Su

Feng-Cheng Yang

Chun-Yuan Chen

Mauricio Manfrini

Wai-Yi Lien

Clement Hsingjen Wann

Chun Hsiung Tsai

Yih Wang

Shahaji B More

Cheng-Yi Peng

Kuo-Feng Yu

Yen-Chieh Huang

Wei-Hao Wu

Zhiqiang Wu

Shih-Lien Linus Lu

Cheng-Tung Huang

Zhi-Chang Lin

Yi-Ching Liu

Ken-Ichi Goto

Ziwei Fang

Jia-Ni Yu

Jia-Ming Chen

Li-Duan Tsai

Chun-Hsiung Tsai

Ya-Ting Chang

Carlos H Diaz

Chia-En Huang

Jean-Pierre Colinge

Ming-Hsi Yeh

Georgios Vellianitis

Yasutoshi Okuno

Sheng-Chih Lai

Kai-Hsuan Lee

Chi-On Chui

Meng-Hsuan Hsiao

Huai-Ying Huang

I-Ming Chang

Kuo-Cheng Chiang

Chih-Hsin Ko

Chung-Wei Hsu

Kuo-Chang Chiang

Ting-Hung Hsu

Yee-Chia Yeo

Yu-Cheng Tung

Chih-Sheng Chang

Li-Te S Lin

Ling-Yen Yeh

Ta-Pen Guo

Hsin-Yen Huang

Chung-Cheng Wu

Samuel C Pan

Marcus Johannes Henricus Van Dal

Yi-Hsun Chiu

Han-Ting Tsai

Chandrashekhar Prakash Savant

Pei-Yu Wang

Wilman Tsai

Chia-Ta Yu

Chi-Lin Teng

Su Xing

Chia-en Huang

Ting-Ya Lo

Kuo-Cheng Ching

Chih-Hao Chang

Shyh-Fann Ting

Chia-Hao Hsu

Yu-Jen Chen

Yi-Tang Lin

Kai-Wen Cheng

Ming-Hsien Lee

Feng-Ching Chu

Tzer-Min Shen

Po-Tsun Liu

Lei-Lung Tsai

Meng-Yi Wu

Wen-Han Hung

Kun-Hsien Lee

Wei-Chih Wen

Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ≤3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ≥7 nm). Ferroelectric layers having larger mean grain sizes may exhibit enhanced crystallinity and a stabilized orthorhombic crystal phase, particularly in relatively thin layers (e.g., ≤15 nm in thickness).

Ferroelectric memory devices having improved ferroelectric properties and methods of making the same

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

Memory chiplet having multiple arrays of memory devices and methods of forming the same

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Three-dimensional memory devices

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Interconnect layout for semiconductor device

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Memory cell and method

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Source/drain metal contact and formation thereof

A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

Semiconductor device with metal cap on gate

A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

Memory circuit and write method

A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The dielectric liner surrounds the conductive structure and is over the top surface of the source/drain contact.

Semiconductor device

A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

Transistor, memory device and manufacturing method of memory device

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Three-dimensional stackable ferroelectric random access memory devices and methods of forming

Semiconductor device structures and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack formed over the substrate. The semiconductor device structure further includes a source/drain structure formed adjacent to the gate stack and a contact structure vertically overlapping the source/drain structure. In addition, the contact structure has a first sidewall slopes downwardly from its top surface to its bottom surface, and an angle between the first sidewall and a bottom surface of the contact structure is smaller than 89.5°.

Semiconductor device structure

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.

Semiconductor device structure and method for forming the same

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Hsinchu, Taiwan

Yu-Ming Lin