Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

United Microelectronics Corp.

Mediatek Corporation

Other

National Taiwan University

Primax Electronics Ltd.

National Yang Ming Chiao Tung University

National Science Council

Parabellum Strategic Opportunities Fund LLC

Chang International Enterprise Co., Ltd.

Yu-Ming Lin

Sai-Hooi Yeong

Chih-Hao Wang

Chia-Hao Chang

Han-Jong Chia

Bo-Feng Young

Jia-Chuan You

Lin-Yu Huang

Cheng-Chi Chuang

Tien-Lu Lin

Meng-Han Lin

Li-Zhen Yu

Chun-Chieh Lu

Chih-Yu Chang

Chung-Te Lin

Sheng-Chen Wang

Chao-I Wu

Chi On Chui

Sheng-Tsung Wang

Chenchen Jacob Wang

Huan-Chieh Su

Hai-Ching Chen

Feng-Cheng Yang

Chun-Yuan Chen

Mauricio Manfrini

Clement Hsingjen Wann

Wai-Yi Lien

Chun Hsiung Tsai

Shahaji B More

Yih Wang

Kuo-Feng Yu

Cheng-Yi Peng

Yen-Chieh Huang

Wei-Hao Wu

Zhiqiang Wu

Shih-Lien Linus Lu

Cheng-Tung Huang

Zhi-Chang Lin

Yi-Ching Liu

Ken-Ichi Goto

Ziwei Fang

Jia-Ni Yu

Jia-Ming Chen

Ming-Hsi Yeh

Li-Duan Tsai

Chun-Hsiung Tsai

Ya-Ting Chang

Carlos H Diaz

Chih-Hsin Ko

Chia-En Huang

Jean-Pierre Colinge

Georgios Vellianitis

Yasutoshi Okuno

Sheng-Chih Lai

Kai-Hsuan Lee

Chi-On Chui

Meng-Hsuan Hsiao

Huai-Ying Huang

I-Ming Chang

Kuo-Cheng Chiang

Chung-Wei Hsu

Chandrashekhar Prakash Savant

Kuo-Chang Chiang

Ting-Hung Hsu

Yee-Chia Yeo

Yu-Cheng Tung

Chih-Sheng Chang

Li-Te S Lin

Ling-Yen Yeh

Ta-Pen Guo

Hsin-Yen Huang

Chung-Cheng Wu

Samuel C Pan

Marcus Johannes Henricus Van Dal

Yi-Hsun Chiu

Han-Ting Tsai

Pei-Yu Wang

Wilman Tsai

Chi-Lin Teng

Chia-Ta Yu

Su Xing

Chia-en Huang

Ting-Ya Lo

Kuo-Cheng Ching

Chih-Hao Chang

Shyh-Fann Ting

Chia-Hao Hsu

Yu-Jen Chen

Yi-Tang Lin

Kai-Wen Cheng

Ming-Hsien Lee

Feng-Ching Chu

Tzer-Min Shen

Meng-Yi Wu

Po-Tsun Liu

Lei-Lung Tsai

Wen-Han Hung

Kun-Hsien Lee

Wei-Chih Wen

A semiconductor chip including a semiconductor substrate, an interconnect structure and memory devices is provided. The semiconductor substrate includes first transistors, and the first transistors are negative capacitance field effect transistors. The interconnect structure is disposed over the semiconductor substrate and electrically connected to the first transistors, and the interconnect structure includes stacked interlayer dielectric layers, interconnect wirings, and second transistors embedded in the stacked interlayer dielectric layers. The memory devices are embedded in the stacked interlayer dielectric layers and electrically connected to the second transistors.

Semiconductor chip

A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.

Three-dimensional memory device and manufacturing method thereof

In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. In the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.

Method of manufacturing a semiconductor device

Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a spacer extending along a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact, a gate contact via over and electrically coupled to the gate structure, and a source/drain contact via over and electrically coupled to the source/drain contact. The gate contact via extends through a first dielectric layer such that a portion of the first dielectric layer interposes between the gate contact via and the spacer. The source/drain contact via extends through a second dielectric layer such that a portion of the second dielectric layer interposes between the source/drain contact via and the liner.

Low parasitic capacitance contact structure

The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

Semiconductor structure with a laminated layer

The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.

Back-end-of-line selector for memory device

A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Dual side contact structures for source/drain regions in semiconductor transistor devices and method of forming

Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ≤3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ≥7 nm). Ferroelectric layers having larger mean grain sizes may exhibit enhanced crystallinity and a stabilized orthorhombic crystal phase, particularly in relatively thin layers (e.g., ≤15 nm in thickness).

Ferroelectric memory devices having improved ferroelectric properties and methods of making the same

A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.

Memory chiplet having multiple arrays of memory devices and methods of forming the same

In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Three-dimensional memory devices

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a substrate, a deep trench capacitor (DTC) having a portion within the substrate, and an interconnect structure over the DTC and the substrate. The interconnect structure includes a seal ring structure in electrical contact with the substrate, a first conductive via in electrical contact with the DTC, and a first conductive line electrically coupling the seal ring structure to the first conductive via.

Interconnect layout for semiconductor device

An improved memory cell architecture including a nanostructure field-effect transistor (nano-FET) and a horizontal capacitor extending at least partially under the nano-FET and methods of forming the same are disclosed. In an embodiment, semiconductor device includes a channel structure over a semiconductor substrate; a gate structure encircling the channel structure; a first source/drain region adjacent the gate structure; and a capacitor adjacent the first source/drain region, the capacitor extending under the first source/drain region and the gate structure in a cross-sectional view.

Memory cell and method

A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Source/drain metal contact and formation thereof

A method includes a gate electrode, a first spacer, a second spacer, a metal cap, and a dielectric structure. The gate electrode is over a substrate. The first spacer structure extends along a first sidewall of the gate electrode. The second spacer structure extends along a second sidewall of the gate electrode. The metal cap is over the gate electrode. The dielectric structure is over the gate electrode, the first spacer structure, and the second spacer structure. The dielectric structure has a top segment higher than a top segment of the metal cap.

Semiconductor device with metal cap on gate

A method of writing data to a memory array of three-terminal memory cells includes simultaneously programming a first subset of memory cells in a first column of the memory array to a first logic level by activating a first select line of the first column and a first bit line of the first column, and simultaneously programming a second subset of memory cells in the first column to the first logic level by activating the first select line and a second bit line of the first column.

Memory circuit and write method

Growing community of inventors

Hsinchu, Taiwan

Yu-Ming Lin