United Microelectronics Corp.

Yu-Lung Shih

Kun-Ju Li

Chau-Chung Hou

Hsin-Jung Liu

Ang Chan

Bin-Siang Tsai

Fu-Yu Tsai

Chun-Tsen Lu

Tai-Cheng Hou

Chih-Yueh Li

Ji-Min Lin

Fu-Shou Tsai

Yang-Ju Lu

Yong-Yi Lin

Ching-Yang Chuang

Chun-Han Chen

Jhih-Yuan Chen

Fu-Chun Hsiao

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ, a passivation layer on the first ULK dielectric layer, and a second ULK dielectric layer on the passivation layer. Preferably, the first ULK dielectric layer includes a first thickness, the passivation layer between the first MTJ and the second MTJ includes a second thickness, the passivation layer on top of the first MTJ includes a third thickness, and the second thickness is greater than the third thickness

Magnetoresistive random access memory and method for fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ; forming a passivation layer on the first ULK dielectric layer, wherein a bottom surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the first MTJ; and forming a second ULK dielectric layer on the passivation layer.

A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Fabricating method of transistors without dishing occurred during CMP process

The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

Method of manufacturing a semiconductor device

An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

Alignment mark structure and method of fabricating the same

A method for manufacturing a memory device is provided, the method includes the following steps: firstly, providing a dielectric layer, then simultaneously forming a contact window and an alignment mark trench in the dielectric layer, wherein the contact window exposes a lower metal line, then forming a conductive layer on the surface of the dielectric layer, in the contact window and in the alignment mark trench, performing a planarization step on the conductive layer, and leaving a residue in the alignment mark trench. Subsequently, a nitrogen plasma step (Nplasma) is performed on the dielectric layer, a cleaning step is performed to remove the residue in the alignment mark trench, and a patterned magnetic tunneling junction, MTJ) film is laminated on the contact window.

Manufacturing method of memory device

Growing community of inventors

Tainan, Taiwan

Yu-Lung Shih