Macronix International Co., Ltd.

Yu-Lien Liu

Shih-Yu Wang

Yan-Yu Chen

Tao-Cheng Lu

Chia-Ling Lu

Che-Shih Lin

An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body.

ESD tolerant I/O pad circuit including a surrounding well

An ESD protection circuit including a substrate of a first conductivity type, an annular well region of a second conductivity type, two first regions of the first conductivity type and at least one transistor of the second conductivity type is provided. The annular well region is disposed in the substrate. The first regions are disposed in the substrate and surrounded by the annular well region. The at least one transistor is disposed on the substrate between the first regions and including a source, a gate, and a drain. The annular well region and the drain are coupled to a first voltage source. The source and one of the first regions are coupled to a second voltage source, and the other of the first regions is coupled to a substrate triggering circuit.

Electrostatic discharge protection circuit

A semiconductor device includes a first well region of a first conductivity type, a second well region of a second conductive type within the first well region. A first region of the first conductivity type and a second region of the second conductivity type are disposed within the second well region. A third region of the first conductivity type and a fourth region of the second conductivity type are disposed within the first well region, wherein the third region and the fourth region are separated by the second well region. The semiconductor device also includes a switch device coupled to the third region.

Methods and structures for electrostatic discharge protection

An RC delay circuit for providing electrostatic discharge (ESD) protection is described. The circuit employs an NMOS transistor and a PMOS transistor to produce a large effective resistance using a relatively small circuit layout area.

Electrostatic discharge protectors having increased RC delays

An electrostatic discharge protection device for protecting an inner circuit, which is operated in a source voltage, is provided and includes a protection unit and a control unit. The protection unit provides a discharge path for transmitting an electrostatic signal from a pad to a ground line. According to a voltage level at a control end, the protection unit adjusts a holding voltage and a triggering voltage determining whether to conduct the discharge path. When the source voltage is supplied, the control unit transmits the input voltage to the control end of the protection unit, so as to raise the holding and the triggering voltages of the discharge path. When the source voltage is not supplied, the control unit switches the control end of the protection unit to a floating condition by the electrostatic signal, so as to lower the holding and the triggering voltages of the discharge path.

Electrostatic discharge protection device and method thereof

A semiconductor device includes a first well region of a first conductivity, a second well region of a second conductivity type, a source region of the second conductivity type within the first well region, and a drain region of the second conductivity type at least partially within the second well region. A well contact to the first well region is coupled to the source. A third doped region of the first conductivity type and a fourth doped region of the second conductivity type are located in the second well region. A first transistor includes the third doped region, the second well region, and the first well region. The first transistor is coupled to a switch device. A second transistor includes the second well region, the first well region, and the source region. The first and the second transistors are configured to provide a current path during an ESD event.

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Hsinchu, Taiwan

Yu-Lien Liu