Lsi Logic Corporation

Yu-Lam Ho

Sheldon Aronowitz

Douglas Ticknor Grider

Gobi R Padmanabhan

James O Kimball

Chi-Yi Kao

Abraham Fong Yee

Yen-Hui Joseph Ku

Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped source region, a lightly doped source region, a gate or channel region, a lightly doped drain region, and a moderately doped drain region, arranged consecutively in that order, with the channel region adjacent to the gate having opposite electrical conductivity type to the electrical conductivity type of the source and drain regions. The source region and drain region are formed by ion implantation with ion kinetic energies of 40 keV or more, to increase the width and depth of charge carrier flow in these regions and to thereby reduce the substrate current associated with the device to less than one &mgr;Amp/&mgr;m. Ion implantation of the source and drain regions with ion kinetic energies of 70 keV or more decreases the hot-electron effect and increases the operating lifetime of the device by a multiplicative factor of 20 or more.

Method of forming source and drain regions for CMOS devices

A silicon semiconductor integrated circuit includes an insulative field oxidation layer which substantially does not encroach under active circuit elements of the integrated circuit. The field oxidation layer is formed of oxidized amorphous silicon created by bombardment of a silicon substrate with noble gas ions. The amorphous silicon oxidizes at a rate much faster than crystalline silicon so that when the field oxidation layer is formed crystalline silicon foundations for the active circuit elements are left substantially intact. The crystalline silicon foundations are formed by using appropriate shield elements during the noble gas ion bombardment. This noble gas ion bombardment also has the advantage of eliminating dislocation defects which may be present in the field oxidation area so that these defects do not propagate into the crystal lattice of the silicon during subsequent heating and cooling cycles. Also, the amorphous silicon relieves surface layer stresses which may be present from prior processes or because of prior morphological structural elements formed on the silicon substrate. A boron ion bombardment may also be used to further inhibit loss of P-well dopant to the oxidant forming the field oxidation layer and preserving a desired high field threshold voltage and robust field isolation for the integrated circuit.

Integrated circuit with isolation of field oxidation by noble gas

A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Substrate with controlled amount of noble gas ions to reduce channeling

A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant,, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.13 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Implantation of a semiconductor substrate with controlled amount of

Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.

Growing community of inventors

Cupertino, CA, United States of America

Yu-Lam Ho