Taiwan Semiconductor Manufacturing Comp. Ltd.

Google Inc.

Yu-Kuan Lin

Ping-Wei Wang

Shih-Hao Lin

Chang-Ta Yang

Chih-Chuan Yang

Hsin-Wen Su

Lien-Jung Hung

Chia-Hao Pao

Lien Jung Hung

Feng-Ming Chang

Jui-Lin Chen

Kuo-Hsiu Hsu

Kian-Long Lim

Ilya Firman

Jasper S Lin

Juliana Tsang

Mark D Womack

Mei-Yun Wang

Kuo-Yi Chao

Chih-Hsuan Chen

Wen-Chun Keng

Sheng Chiang Hung

Choh Fei Yeap

Jakob David Uszkoreit

Kirill Buryak

Trausti T Kristjansson

Huai-Ying Huang

Yusuke Konishi

Joshua James Estelle

Kuo-Hung Lo

Shau-Wei Lu

Jordan Hsu

John Huang

Sheng-chi Hsieh

Hung-ying Tyan

Chung-Yi Wang

Chien-Yuan Chen

Chih-Wei Lee

Yung-Hsiang Chan

Jo-Chun Hung

Sheng-Chi Hsieh

Chia-En Huang

Chia-en Huang

Chao-Yuan Chang

Chung-yih Wang

Huai-Yang Huang

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.

High-k gate dielectric

A method includes providing a substrate, a source/drain (S/D) feature and semiconductor channel layers over the substrate, a high-k metal gate (HKMG) wrapping around the channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL. The channel layers are spaced one from another along a direction perpendicular to a top surface of the substrate and connect to the S/D feature. The method further includes etching the ILD layer and the CESL to expose a top portion of the S/D feature; etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the channel layers; and forming a metallic contact in the S/D contact trench.

Method and structure for gate-all-around devices with deep S/D contacts

A memory device includes a substrate, an active region, a first gate structure, a second gate structure, a first word line, and a second word line. The active region protrudes from a top surface of the substrate. The active region has at least one ring structure, in which when viewed from above, the ring structure has a first linear portion, a second linear portion, a first curved portion, and a second curved portion, the first curved portion connects first sides of the first and second linear portions, and the second curved portion connects second sides of the first and second linear portions. The first gate structure and the second gate structure are over the substrate and cross the active region. The first word line and the second word line are electrically connected to the first gate structure and the second gate structure, respectively.

Memory device and method for forming the same

A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

Macro and SRAM bit cell cooptimizatoin for performance (long/shortwordline combo SRAM)

A method includes forming an anti-punch-through layer over a first region and a second region of a substrate, forming a semiconductor layer over the anti-punch-through layer, patterning the semiconductor layer and the anti-punch-through layer to form a first plurality of fins over the first region and a second plurality of fins over the second region, and forming a patterned resist layer over the first plurality of fins and the second plurality of fins. The method also includes recessing a portion of the substrate between the first plurality of fins and the second plurality of fins in an etching process through openings of the patterned resist layer.

Crown bulk for FinFET device

Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.

Static random access memory with magnetic tunnel junction cells

An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.

Compact electrical connection that can be used to form an SRAM cell and method of making the same

A method includes receiving a workpiece. The workpiece includes a first dummy gate, a second dummy gate adjacent the first dummy gate, a first gate spacer disposed along sidewalls of the first dummy gate, and a second gate spacer disposed along sidewalls of the second dummy gate. The method further includes removing the first dummy gate and the second dummy gate to form a first gate trench and a second gate trench, respectively, enlarging the first gate trench and the second gate trench, forming a first metal gate structure in the enlarged first gate trench, and forming a second metal gate structure in the enlarged second gate trench. The enlarged second gate trench is wider than the enlarged first gate trench.

Semiconductor memory structure

A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming a first gate structure over the substrate and crossing the first semiconductor fin; forming a second gate structure over the substrate and crossing the second semiconductor fin; forming a first gate spacer on a sidewall of the first gate structure; and forming a second gate spacer on a sidewall of the second gate structure, wherein in a top view, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer in contact with the first gate structure is misaligned with an inner sidewall of the second gate spacer in contact with the second gate structure.

A device includes a substrate, a contact, a first gate, a second gate, a dielectric feature between the gates, a via, and a conductive line. The gates are each adjacent the contact and aligned lengthwise with each other along a first direction. A first sidewall of the dielectric feature defines an end-wall of the first gate. A second sidewall of the dielectric feature defines an end-wall of the second gate. The conductive line extends along a second direction. A projection of the conductive line onto a top surface of the dielectric feature passes between the first and second sidewalls. The via interfaces with the contact along a second plane. The via has a first dimension on the second plane along the second direction; the contact has a second dimension on the second plane along the second direction. The first dimension is greater than the second dimension.

Integrated circuit device with reduced via resistance

A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.

Semiconductor device including alternating semiconductor layers with different widths and method for forming the same

A memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The first gate structure crosses the first semiconductor fin. The second gate structure crosses the second semiconductor fin, the first gate structure extending continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.

Structure and method for multigate devices with suppressed diffusion

A semiconductor device includes a memory macro having a middle strap area between edges of the memory macro and memory bit areas on both sides of the middle strap area. The memory macro includes n-type wells and p-type wells arranged alternately along a first direction with well boundaries between the adjacent n-type and p-type wells. The n-type and the p-type wells extend lengthwise along a second direction and extend continuously through the middle strap area and the memory bit areas. The memory macro includes a first dielectric layer disposed at the well boundaries in the middle strap area and the memory bit areas. From a top view, the first dielectric layer extends along the second direction and fully separates the n-type wells from the p-type wells in the middle strap area. From a cross-sectional view, the first dielectric layer vertically extends into the n-type or the p-type wells.

Cut metal gate in memory macro edge and middle strap

A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

Gate-all-around semiconductor device and method

Growing community of inventors

Taipei, Taiwan

Yu-Kuan Lin