Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Other

Rhymebus Corporation

Yu-Hung Lin

Sheng-Hsuan Lin

Chih-Wei Chang

You-Hua Chou

Yu-Min Chang

Horng-Huei Tseng

Chi-Wen Liu

Chia-Lin Hsu

Der-Chyang Yeh

An-Jhih Su

Chun-Hsien Huang

Kuei-Pin Lee

Chia-Nan Yuan

Hon-Lin Huang

Ming-Shih Yeh

Mei-Hui Fu

Shih-Guo Shen

I-Tseng Chen

Hung-Wen Su

Wei-Jung Lin

Ya-Lien Lee

Shih-Chi Lin

Ching-Fu Yeh

Yao-Hsiang Liang

Shih-Peng Tai

Wei-Ming Wang

Chi-Yu Chou

Chen-Kuang Lien

Yu-Chang Hsiao

Chen-Hua Douglas Yu

Szu-Wei Lu

Kuo-Chung Yee

Ying-Ching Shih

Chih-Wei Wu

Li-Wei Chu

Ming Shih Yeh

Kuan-Ta Chen

Hung-Chang Hsu

Hsuan-Yu Huang

Yu-Shiuan Wang

Cheng-Tse Chang

Shun-Han Ko

Hsien-Tang Jao

Sung-Han Wen

Rueijer Lin

Chih-Hsin Chen

Yao Hsiang Liang

Shih-Hsiung Chien

Hsin-Chen Tsai

Po-Chun Chiu

Chiu-Hsiung Chen

Yu-Hsiao Lin

Chi-Heng Chung

The present invention provides an amplifier including an input stage, an amplifier stage, a power stage and a de-gain stage. The input stage is configured to receive an input signal to generate an amplified signal. The amplifier stage is configured to generate a first driving signal and a second driving signal according to the amplified signal. The power stage comprises a first input terminal and a second input terminal, wherein the power stage is coupled to a supply voltage and a ground voltage, for receiving the first driving signal and the second driving signal from the first input terminal and the second input terminal, respectively, and generating an output signal.

High-efficiency amplifier architecture with de-gain stage

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor die, a semiconductor frame structure, a semiconductor cover structure and conductive balls. The substrate has a ground plate embedded therein. The semiconductor die is disposed on the substrate and electrically connected with the substrate. The semiconductor frame structure is disposed on the substrate and surrounds the semiconductor die. The semiconductor frame structure includes conductive through semiconductor vias (TSVs) penetrating through the semiconductor frame structure, and at least one conductive TSV is electrically connected with the ground plate. The semiconductor cover structure is disposed on the semiconductor frame structure and on the semiconductor die. The semiconductor cover structure includes a conductive grid pattern and the conductive grid pattern contacts the conductive TSVs. The conductive balls are disposed on the substrate and electrically connected with the semiconductor die through the substrate.

Semiconductor package and manufacturing method thereof

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

Semiconductor structure having through substrate via and manufacturing method thereof

In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Semiconductor device and method

A method of manufacturing a semiconductor device includes the following steps. A semiconductor substrate is provided. A plurality of dielectric layers and a plurality of first conductive features in the dielectric layers are formed on the semiconductor substrate. At least one polymer layer and a plurality of second conductive features in the at least one polymer layer on the dielectric layers are formed. A plurality of conductive connectors are formed to electrically connect to the second conductive features. The semiconductor substrate, the dielectric layers and the at least one polymer layer are cut into a plurality of dies.

Methods of manufacturing semiconductor devices

A sensing rack includes a base, a plurality of sensing mechanisms, and a plurality of displaying elements. The base includes a plurality of accommodating spaces. The sensing mechanisms are disposed in the base, and each of the sensing mechanisms correspond to each of the accommodating spaces and includes a light sensing component and a light blocking element. A light sensing component includes a light emitting element and a light receiving element. The light blocking element is drivable to move between the light emitting element and the light receiving element so as to control a light of the light emitting element to enter the light receiving element or not. Each of the displaying elements is electrically connected with the light receiving element of each of the sensing mechanisms and is for displaying the light of each of the light emitting elements entering the light receiving element or not.

Sensing rack and sensing rack set

A semiconductor device includes an integrated circuit structure and a thermal pillar over the integrated circuit structure. The integrated circuit structure includes a semiconductor substrate including circuitry, a dielectric layer over the semiconductor substrate, an interconnect structure over the dielectric layer, and a first thermal fin extending through the semiconductor substrate, the dielectric layer, and the interconnect structure. The first thermal fin is electrically isolated from the circuitry. The thermal pillar is thermally coupled to the first thermal fin.

Thermal structure for semiconductor device and method of forming the same

A package structure and method of forming the same are provided. The package structure includes a first die and a second die disposed side by side, a first encapsulant laterally encapsulating the first and second dies, a bridge die disposed over and connected to the first and second dies, and a second encapsulant. The bridge die includes a semiconductor substrate, a conductive via and an encapsulant layer. The semiconductor substrate has a through substrate via embedded therein. The conductive via is disposed over a back side of the semiconductor substrate and electrically connected to the through substrate via. The encapsulant layer is disposed over the back side of the semiconductor substrate and laterally encapsulates the conductive via. The second encapsulant is disposed over the first encapsulant and laterally encapsulates the bridge die.

Package structure with bridge die laterally wrapped by insulating encapsulant and surrounded by through vias and method of forming the package structure

A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.

Semiconductor devices

A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Metal contact structure and method of forming the same in a semiconductor device

An array controlling system includes a database, a controlling center and an array device. The controlling center reads a plurality of data of the database. The array device includes a processing unit, a main bus and an array unit. The processing unit receives a command of the controlling center and converts the command into a communication data. The main bus is configured to transmit the communication data to the array unit. A plurality of array modules of the array unit are connected in series with each other through a serial bus, and sequentially receive the communication data. The processing unit controls each of the array modules according to the communication data. A plurality of sensing data of the array modules are collected to the processing unit. The processing unit returns the sensing data to the database or the controlling center to update the database.

Array controlling system for controlling multiple array modules and controlling method thereof

A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

Interconnection structure, fabricating method thereof, and semiconductor device using the same

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

An operational amplifier includes a single-stage amplifier and a current controller. The single-stage amplifier receives an input signal, and amplifies the input signal to generate an output signal, wherein the single-stage amplifier includes a voltage controlled current source circuit that operates in response to a bias voltage input. The current controller receives the input signal, and generates the bias voltage input according to the input signal. The bias voltage input includes a first bias voltage, a second bias voltage, a third bias voltage, and a fourth bias voltage. None of the first bias voltage, the second bias voltage, the third bias voltage, and the fourth bias voltage is directly set by the input signal of the single-stage amplifier.

Operational amplifier using single-stage amplifier with slew-rate enhancement and associated method

The present invention provides a circuit applied to a bio-information acquisition system, wherein the circuit includes a terminal, an output circuit, a feedback circuit and a calibration circuit. In the operations of the circuit, the terminal is arranged to receive an input signal, the output circuit is configured to generate an output signal according to the input signal, the feedback circuit is configured to receive the output signal to generate a current signal to the terminal, and the calibration circuit is configured to generate a control signal to control the feedback circuit to determine a level of the current signal according to the output signal.

Circuit applied to bio-information acquisition system

Growing community of inventors

Taichung, Taiwan

Yu-Hung Lin