Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Huei Chen

Chen-Hua Douglas Yu

Syun-Ming Jang Jang

Lain-Jong Li

Yu-Liang Lin

Henry Lo

Ai-Sen Liu

Ping-Hsu Chen

Ping Chuang

Sung-Ming Jang

Shang-Ting Tsai

Chao-Jung Chang

Yung-Cheng Lu

Chung-Chi Ko

Lih-Ping Li

Yao-Yi Cheng

Shu-E Ku

In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

EBR shape of spin-on low-k material providing good film stacking

A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.

Method and system for in-situ monitoring of mixing ratio of high selectivity slurry

This invention provides a method to improve the adhesion between dielectric material layers at the interface thereof, during the manufacture of a semiconductor device. The first step is to form a SiC-based dielectric material layer over a substrate. The SiC-based dielectric material layer is treated by oxygen plasma. A second layer of dielectric material is formed over the SiC-based dielectric material layer.

Method for improving adhesion between dielectric material layers

A method for forming a capping layer for improved adhesion with an underlying insulating layer in a multiple layer semiconductor device manufacturing process including providing a semiconductor wafer including a process surface comprising a dielectric insulating layer; and, providing a capping layer overlying the dielectric insulating layer according to a chemical vapor deposition CVD) process. The capping layer of the present invention has improved adhesion and a reduced dielectric constant with comparable current leakage compared to capping layers of the prior art.

Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant

Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

Dual damascene aperture formation method absent intermediate etch stop layer

Growing community of inventors

Hsin-Chu, Taiwan

Yu-Huei Chen