Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Semiconductor Manufacturing Company

Yu-Hua Lee

Cheng-Ming Wu

Wen-Chuan Chiang

James Cheng-Ming Wu

Jenn Ming Huang

James (Cheng-Ming) Wu

Min-Hsiung Chiang

Chia-Hung Lai

Chin-Tien Yang

Tse-Liang Ying

Cheng-Yeh Shih

Kuo Ching Huang

Huan-Chi Tseng

Ming-Hsiung Chiang

Min Cao

Tzong-Sheng Chang

Jiunn-Jyi Lin

Yung-Kuan Hsiao

Tze-Liang Ying

Chia-Shiung Tsai

Yen-Ming Chen

Chao-Cheng Chen

Dian-Hau Chen

Kuo-Ching Huang

Chine-Gie Lou

Cheng-Tung Lin

Kang-Min Kuo

Chao-Ming Koh

Daniel Hao-Tien Lee

Mu-Yi Lin

Ming-Hsin Li

Juan-Jann Jou

Yu-Wei Tseng

Min Ca

Cheng Ming Wu

A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.

Key-hole free process for high aspect ratio gap filling with reentrant spacer

A method for fabricating a microelectronic fabrication employs an undoped silicate glass layer as an etch stop layer when etching a doped silicate glass layer with an anhydrous hydrofluoric acid etchant. The method is particularly useful for forming a patterned salicide blocking dielectric layer when fabricating a complementary metal oxide semiconductor device.

Laminated silicate glass layer etch stop method for fabricating microelectronic product

A method for manufacturing a dual damascene structure, which forms a trench first, is described. The manufacturing method has following steps. First, a substrate with a plurality of semiconductor devices is provided. A first metal layer, a first etching stop layer, a dielectric layer, and a second etching stop layer are subsequently formed thereon. A trench is formed in the dielectric layer at a predetermined depth thereafter, and a sacrificial layer is filled therein and is next planarized. Then a photoresist layer is formed thereon for etching a via. Afterward the photoresist layer and the sacrificial layer are both removed. Following that, the first etching stop layer is etched through to expose the first metal layer. Finally, the via and the trench are filled with a second metal layer.

Method for manufacturing dual damascene structure with a trench formed first

A novel method of forming a bond pad of a semiconductor device and a novel bond pad structure. Two passivation layers are used to form bond pads of a semiconductor device. A portion of the second passivation layer resides between adjacent bond pads, preventing shorting of the bond pads during subsequent wire bonding processes or flip-chip packaging processes.

Bond pad scheme for Cu process

A dual bit ROM multilayered structure with improved write and erase functions and a method of manufacturing is disclosed. The structure includes a pair of floating gates at the middle or nitride layer to better define the two locations of electrons representing the dual data bits collected in the middle layer.

Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing

A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 &angst; to about 500 &angst; and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 &angst; to about 1200 &angst; below the narrow neck.

Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule

A method of using resist planarization to prepare for silicidation while protecting silicon nitride spacers in the fabrication of integrated circuits is described. Field oxide areas are formed on a semiconductor substrate surrounding and electrically isolating a logic device area and a memory device area. Polysilicon gate electrodes having silicon nitride sidewall spacers and associated source/drain regions are formed in the device areas. A silicon oxide layer is deposited overlying the gate electrodes and source/drain regions. The silicon oxide layer is covered with a photoresist layer. The photoresist layer is developed until the silicon oxide layer overlying the gate electrodes is exposed and the photoresist layer is below the tops of the gate electrodes. The exposed silicon oxide layer is etched away whereby the tops of the gate electrodes are exposed and wherein the silicon nitride spacers are undamaged by the etching. All of the silicon oxide layer in the logic device area is etched away. A layer of titanium is deposited over the semiconductor substrate which is annealed to transform the titanium layer into a titanium silicide layer over the gate electrodes and over the source/drain regions in the logic area. The unreacted titanium layer is removed to leave the titanium silicide layer only on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source/drain regions associated with the gate electrodes in the logic device area.

Simple photo development step to form TiSix gate in DRAM process

A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask. A passivation layer is deposited overlying the conductive layer and the dielectric layer. The integrated circuit device is completed.

Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids

A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.

Process for making embedded DRAM circuits having capacitor under bit-line (CUB)

A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO ) first insulating layer is formed over device areas, and a first silicon nitride (Si N ) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si N layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si N layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si N layers prevent etching of the underlying first SiO layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si N layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.

Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)

A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings. The openings in the first and second etch-stop layers are both extended by etching the second and first dielectric layers, respectively, until the former opening reaches the second etch-stop layer, and the latter reaches the underlying substructure of devices within the semiconductor substrate. Thus, a combination of contact via interconnects, without borders, and self-aligned with respect to metal lines with relaxed photolithographic tolerances is formed together and simultaneously using a modified dual damascene process having two etch-stop layers.

Borderless dual damascene contact

This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 &angst; to about 500 &angst; and the gap has a deep, pocket-like cross-section with a width from about 500 &angst; to about 1,200 &angst; below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.

Growing community of inventors

Hsinchu, Taiwan

Yu-Hua Lee