United Microelectronics Corp.

Institute for Information Industry

Other

Industrial Technology Research Institute

Usi Corporation

Yu-Hsiang Lin

Chih-Kai Hsu

Ssu-I Fu

Chin-Hung Chen

Chun-Ya Chiu

Chia-Jung Hsu

Chi-Ting Wu

Yu-Ruei Chen

Zen-Jay Tsai

Sheng-Yao Huang

Yu-Hsiang Hung

Chung-Liang Chu

Ming-Hua Tsai

Chien-Ting Lin

Tsai-Yu Wen

Yu-Ping Wang

Shih-Hung Tsai

Jyh-Shyang Jenq

Chien-Hao Chen

Hsuan-Hsu Chen

Chih-Hsiang Ho

Chun-Hsien Lin

Chih-Sheng Chang

Wen-Fang Lee

Jia-Rong Wu

Chiu-Te Lee

Chung-Fu Chang

Nien-Chung Li

Po-Wen Su

Ching-Chung Yang

Yi-Wen Chen

Rong-Hong Jan

Chia-Wei Liu

Jung Han

Chih-Mou Lin

Tzu-Lang Shih

Ming-Chi Li

Po-Wen Chi

Zi-Tsan Chou

Chung-Sung Chiang

Lieh-Hsiung Hu

Shi You Liu

Ching-Lun Lin

Yi-Han Ye

Wei-Chih Lin

Shin-Hung Li

Chun-Tsen Lu

Po-Kuang Hsieh

Yu-Hsiu Chang

Chang-Po Hsiung

Shih-Chang Huang

Nae-Lih Wu

Shan-Shi Huang

Heng-Iang Hsu

Yu-Ting Tseng

Jun-Chi Huang

Chien Sheng Chen

Hung-Chun Wu

Hung-Yi Wu

Wei-Chih Chen

Kuan-Hao Tseng

Jia-Feng Fang

Ching-Hsiang Chiu

Guang-Yu Lo

Yung-Shen Chang

Hao-Yeh Liu

Che-Wei Chu

Ching-Chi Hsu

Jia-He Lin

Tung-Ming Chen

Chih-Jen Lin

Jing-Wei Guo

Lee-Jen Lu

Chung-Hsien Tsai

Chun Yu Chen

Chun-Fan Hsieh

A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

Integrated high, medium, and low voltage semiconductor devices and method for fabricating the same

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Manufacturing method of semiconductor device including gate oxide layer

A semiconductor device includes a substrate, a buried oxide layer in the substrate and near a surface of the substrate, a gate dielectric layer on the substrate and covering the buried oxide layer, a gate structure disposed on the gate dielectric layer and overlapping the buried oxide layer, a source region and a drift region in the substrate and respectively at two sides of the gate structure, wherein the drift region partially covers a lower edge of the buried oxide layer and exposes a side edge of the buried oxide layer, and a drain region in the drift region.

High voltage semiconductor device including buried oxide layer

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is even with a top surface of the fin-shaped structure.

Method for integrating high-voltage (HV) device, medium-voltage (MV) device, and low-voltage (LV) device

A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Semiconductor device and method of fabricating the same

A bonded semiconductor structure includes a first device wafer and a second device wafer. The first device includes a first dielectric layer, a first bonding pad disposed in the first dielectric layer, and a first bonding layer on the first dielectric layer. The second device wafer includes a second dielectric layer, a second bonding layer on the second dielectric layer, and a second bonding pad disposed in the second dielectric layer and extending through the second bonding layer and at least a portion of the first bonding layer. A conductive bonding interface between the first bonding pad and the second bonding pad and a dielectric bonding interface between the first bonding layer and the second bonding layer include a step-height in a direction perpendicular to the dielectric bonding interface and the conductive bonding interface.

Bonded semiconductor structure utilizing concave/convex profile design for bonding pads

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

Semiconductor device including gate oxide layer

A recyclable crosslinked polymeric foam includes a reaction product of 0.1 to 10 parts by weight of a crosslinking agent and 0.1 to 5 parts by weight of a radical initiator, based on 100 parts by weight of a polymeric material. The crosslinking agent is represented by the following formula: wherein R is an alkylene group having 2 to 10 carbon atoms, an arylene group having 6 to 18 carbon atoms, or a cycloalkylene group having 6 to 18 carbon atoms.

Recyclable crosslinked polymeric foam and applications thereof

A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.

A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

Growing community of inventors

Taipei, Taiwan

Yu-Hsiang Lin