Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Parabellum Strategic Opportunities Fund LLC

Yu-Hsiang Hu

Hung-Jui Kuo

Sih-Hao Liao

Po-Han Wang

Chen-Hua Douglas Yu

Chung-Shi Liu

Wei-Chih Chen

Yung-Chi Chu

Ming-Da Cheng

Hung-Chun Cho

Zi-Jheng Liu

Jhih-Yu Wang

Wei-Yu Chen

Meng-Che Tu

Wei-Hung Lin

Jo-Lin Lan

Tian Hu

Ting-Chen Tseng

Hao-Yi Tsai

Chen-Cheng Kuo

Meng-Wei Chou

Chewn-Pu Jou

Hung-Yi Kuo

Tsung-Yuan Yu

Li-Hsien Huang

Cheng-Chieh Hsieh

Yi-Wen Wu

Wan-Yu Lee

Chung-Ming Weng

Hua-Wei Tseng

Yueh-Ting Lin

Hua-Kuei Lin

Chiang Lin

Hsiu-Jen Lin

Chien-Hsun Lee

Tsung-Ding Wang

Ming-Che Ho

Hao-Cheng Hou

Shih-Peng Tai

Jung-Wei Cheng

Cheng-Tse Tang

Hung-Jui Kou

I-Chia Chen

Chih-Wei Lin

Feng-Wei Kuo

Ming Hung Tseng

Hsin-Yu Pan

Tsung-Hsien Chiang

Tzu-Sung Huang

Po-Yuan Teng

Chien-Hsun Chen

Kuo-Lung Pan

Chen-Fa Lu

Shu-Rong Chun

Ban-Li Wu

Mao-Yen Chang

Yi-Che Chiang

Wei-Kang Hsieh

Ting Hao Kuo

Cheng-Chieh Wu

Shih-Hao Liao

Pavithra Sriram

Ming-da Cheng

An integrated fan-out (InFO) package includes a die, an encapsulant laterally encapsulating the die, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns and a plurality of alignment marks. The routing patterns are electrically connected to the die. The alignment marks surround the routing patterns. The alignment marks are electrically insulated from the die and the routing patterns. At least one of the alignment marks is in physical contact with the encapsulant, and the alignment marks located at different level heights are arranged in a non-overlapping manner vertically.

Integrated fan-out package and manufacturing method thereof

A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

Package structure and method of manufacturing the same

A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

Dielectric slots underneath conductive vias in interconnect structure of semiconductor package and method of forming the same

A passivation layer and conductive via are provided, wherein the transmittance of an imaging energy is increased within the material of the passivation layer. The increase in transmittance allows for a greater cross-linking that helps to increase control over the contours of openings formed within the passivation layer. Once the openings are formed, the conductive vias can be formed within the openings.

Methods of manufacture having redistribution layer using dielectric material photoactive component

In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Integrated circuit packages having adhesion layers for through vias

A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

Redistribution structure for semiconductor device and method of forming same

A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

Semiconductor device and manufacturing method thereof

A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Semiconductor package and method for manufacturing the same

A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

Semiconductor device and method of fabricating the same

A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.

Package structure including auxiliary dielectric portion

A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure partially exposes the die. A top surface of the redistribution structure is slanted downward continuously from an edge of the package toward an interior of the package.

Package and manufacturing method thereof

A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.

Lithography

A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Semiconductor package and method of forming the same

A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.

A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.

Polymer material in a redistribution structure of a semiconductor package and method of manufacture

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Hsinchu, Taiwan

Yu-Hsiang Hu