Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Yu-Chun Chang

Po-Wei Liu

Cheng-Ta Wu

Chia-Ta Hsieh

Hung-Ling Shih

Yu-Hung Cheng

Chen-Ming Huang

Wen-Tuo Huang

Tsung-Yu Yang

Yu-Ling Hsu

Shih-Hsien Chen

Chia-Sheng Lin

Yu-Wen Tseng

ShihKuang Yang

Wei-Lin Chang

Tsung-Hua Yang

Yu-Hsiang Yang

Ying Ling Tseng

Kuo Wei Wu

Yeur-Luen Tu

Ru-Liang Lee

Yun-Chi Wu

Ching I Li

Ping-Cheng Li

Kan-Sen Chou

Yu-Chieh Lu

Yi-Chu Chen

Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.

Semiconductor-on-insulator (SOI) substrate and method for forming

A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.

ONON sidewall structure for memory device and method for making the same

A method for eliminating divot formation includes forming an isolation layer; forming a conduction layer which has an upper inclined boundary with the isolation layer such that the conduction layer has a portion located above a portion of the isolation layer at the upper inclined boundary; etching back the isolation layer; and etching back the conduction layer after etching back the isolation layer such that a top surface of the etched conduction layer is located at a level lower than a top surface of the etched isolation layer.

Method for eliminating divot formation and semiconductor device manufactured using the same

In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.

Selective polysilicon growth for deep trench polysilicon isolation structure

ONON sidewall structure for memory device and methods of making the same

A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Semiconductor isolation structure and method of making the same

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

Multilayer isolation structure for high voltage silicon-on-insulator device

Various embodiments of the present application are directed towards a method for forming a semiconductor-on-insulator (SOI) substrate with a thick device layer and a thick insulator layer. In some embodiments, the method includes forming an insulator layer covering a handle substrate, and epitaxially forming a device layer on a sacrificial substrate. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates, and the sacrificial substrate is removed. The removal includes performing an etch into the sacrificial substrate until the device layer is reached. Because the device layer is formed by epitaxy and transferred to the handle substrate, the device layer may be formed with a large thickness. Further, because the epitaxy is not affected by the thickness of the insulator layer, the insulator layer may be formed with a large thickness.

The present invention relates to a continuous reactor a method for manufacturing nanoparticles. The reactor of the present invention includes: a plurality of first inputs for individually inputting a plurality of reagents; a first mixing part connected to the first inputs to mix the reagents; N number of first reaction units, each comprising a plurality of first diverging channels and a first converging channel to form a channel having the first diverging channels and the first converging channels alternately connected to one another in series for N times of diverging-converging actions, wherein N&#x2267;1, and the first diverging channels of a 1one of the first reaction units are connected to the first mixing part; and a first output connected to the first converging channel of an None of the first reaction units, so as to output a product of nanoparticles.

Continuous reactor and method for manufacturing nanoparticles

Growing community of inventors

Hsinchu, Taiwan

Yu-Chun Chang