Nan Ya Technology Corporation

Yu-Chi Sun

Tse-Yao Huang

Shing-Yih Shih

Chih-Ching Lin

Chao-Wen Lay

Chang Rong Wu

A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C F and CHF , and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.

Etch-back method for dielectric layer

A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.

Method for fabricating floating gate

A memory cell fabrication avoiding bit line encroaching. A first insulating layer and a first masking layer are formed on a semiconductor substrate with a diffused region. The first masking layer and the first insulating layer are defined to form a first trench above the diffusion region. A second masking layer is formed to fill the first trench, and a hole is formed by removing a portion of the second masking layer above the diffusion region. A bit line contact is formed by removing a portion of the first insulating layer beneath the hole to expose the diffusion region. A bit line contact plug is formed by filling the bit line contact with a first conductive layer. The residual second masking layer and the first masking layer are removed to form a second trench. A bit line is formed by filling the second trench with a second conductive layer.

Method of fabricating bit line and bit line contact plug of a memory cell

A method of forming interconnects. An oxide masking layer with patterns is formed overlaying the metal layer. The patterns of the masking layer are transferred into the metal layer so as to form an opening. Then, a silicon nitride liner is conformally formed on the masking layer, the metal layer and the first insulating layer. Next, the silicon nitride liner and the masking layer are partially removed by reactive ion etching to leave a facet mask to reduce the aspect ratio of the opening followed by removal of the remaining silicon nitride liner. Then, an insulating layer is deposited to fill the opening.

Growing community of inventors

Taoyuan, Taiwan

Yu-Chi Sun