Taiwan Semiconductor Manufacturing Comp. Ltd.

Yu-Chang Liang

Kao-Ting Lai

Chun-Hao Hsu

Yu-Chun Ko

Li-Yi Chen

Ru-Shang Hsiao

Chien-Hsun Lin

Sheng-Fu Yu

Kuan Yu Chen

Jhon Jhy Liaw

Kuo-Hua Pan

Ta-Chun Lin

Chun-Jun Lin

Jyun-Yang Shen

Ming-Che Chen

A method for manufacturing a semiconductor device is provided. The method includes forming first and second semiconductor fins; forming first and second gate structures respectively over first regions of the first and second semiconductor fins; forming a first dummy spacer at a sidewall of the first gate structure adjacent a second region of the first semiconductor fin; etching a first source/drain recess in the second region of the first semiconductor fin; forming a n-type source/drain epitaxial structure in the first source/drain recess; forming a second dummy spacer at a sidewall of the second gate structure adjacent a second region of the second semiconductor fin, wherein the second dummy spacer has a thickness less than that of the first dummy spacer; etching a second source/drain recess in the second region of the second semiconductor fin; and forming a p-type source/drain epitaxial structure in the second source/drain recess.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Finfet with dummy fins and methods of making the same

FinFET with dummy fins and methods of making the same

A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

A semiconductor structure includes semiconductor fins protruding out of a substrate, dielectric fins protruding out of the substrate and disposed among the semiconductor fins, and gate stacks disposed over the semiconductor fins and the dielectric fins. The dielectric fins include a first dielectric material layer, a second dielectric material layer disposed over the first dielectric material layer, and a third dielectric material layer disposed over the second dielectric material layer, where the first and second dielectric material layers have different compositions and the first and the third dielectric material layers have the same compositions.

A FinFET device includes a dielectric layer formed over a semiconductor substrate and having an upper dielectric layer surface. A fin of semiconductor material extends upwards from the substrate through an opening in the dielectric layer. A base portion of the fin, which is recessed below the upper dielectric layer surface, includes a base channel region that separates first and second base source/drain regions. An upper channel region extends upwards from the base channel region and terminates in an upper fin surface disposed above the upper dielectric layer surface. A gate electrode straddles the upper channel region and is separated from the upper channel region by a gate dielectric. First and second epitaxial source/drain regions meet the first and second base source/drain regions, respectively, at first and second interfaces, respectively. The first and second interfaces are recessed in the opening and arranged below the upper dielectric layer surface.

Fin sidewall removal to enlarge epitaxial source/drain volume

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Kaohsiung, Taiwan

Yu-Chang Liang