International Business Machines Corporation

Youngseok Kim

Soon-Cheon Seo

Injo Ok

Alexander Reznicek

Takashi Ando

Hiroyuki Miyazoe

Dexin Kong

Timothy Mathew Philip

Choonghyun Lee

Joel Pereira De Souza

Babar Ali Khan

Eduard Albert Cartier

Chun-Chen Yeh

Don Greenberg

Abhinav Kandala

Daniel Josef Egger

Douglas T McClure, Iii

Sarah Elizabeth Sheldon

Devendra K Sadana

Lawrence Alfred Clevenger

Steven J Holmes

Theodorus E Standaert

Oleg Gluschenkov

Vijay Narayanan

Christopher J Penny

Robert Russell Robison

Nicholas Anthony Lanzillo

Seyoung Kim

Xiao Lin Sun

Paul Charles Jamison

Kevin W Brew

Nicole A Saulnier

Shyng-Tsong Chen

Lan Yu

Wei Wang

Jungwook Choi

Andrew W Cross

Sagarika Mukesh

Paul Kristan Temme

Iqbal Rashid Saraf

Antonio Corcoles-Gonzalez

Maika Takita

Ewout Van Den Berg

Neereja Sundaresan

Theodore James Yoder

Xuan Wei

Jonas Doevenspeck

Edward Hong Chen

Andrew Eddins

Timothy Matthew Philip

A method, system and computer program product for calibrating a quantum operation. Layers of two qubit gates that operate in parallel are defined. A gate length for each two qubit gate in a layer of the defined layers is calibrated to correspond to the same gate length, such as the gate length of the two qubit gate in that layer with the slowest operation speed. A portion of the quantum operation is performed by the two qubit gates in the layer with the calibrated gate length. In this manner, two qubit gates that operate in parallel are effectively calibrated in a manner that results in better gate fidelities, fewer frequency collisions and fewer undesirable transitions.

Calibration of two qubit gates involved in parallel operations

A resistive memory includes: a bottom electrode; a first contact on the bottom electrode; a switching material pad on the first contact, wherein the switching material pad includes an oxide and a plurality of current conducting filaments in the oxide; a top electrode on the switching material pad; a plurality of sacrificial vias contacting the bottom electrode; a second contact that is connected to the bottom electrode; and a third contact that is connected to the top electrode.

Redundant bottom pad and sacrificial via contact for process induced RRAM forming

A system comprises a memory that stores and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise an execution component that directs execution, employing a quantum processor, of an error mitigation set of quantum circuits that were noise-adjusted by employing noise scaling, and an evaluation component that evaluates, at an evaluation, results of the execution of the error mitigation set of quantum circuits, wherein the evaluation comprises a first generation of a first average expectation value corresponding to a noise-attenuated result of the execution, and wherein the evaluation further comprises a second generation of a second average expectation value corresponding to a noise-amplified result of the same execution.

Probabalistic amplification and attenuation of quantum errors using a single dataset

Embodiments of present invention provide a method of forming a resistive random-access memory (RRAM). The method includes forming a dielectric layer on top of a supporting structure, wherein the dielectric layer has a bottom electrode embedded therein; forming an oxide layer on top of the bottom electrode; treating the oxide layer in a plasma environment; forming a top electrode on top of the oxide layer; forming a first interlevel-dielectric (ILD) layer on top of the top electrode; forming a via contact and a first metal layer in the first ILD layer, wherein the first metal layer is in contact with the top electrode through the via contact; forming a capping layer on top of the first metal layer through a plasma-enhanced deposition process; and causing formation of one or more filaments in the oxide layer during the plasma-enhanced deposition process. A structure of the RRAM is also provided.

Process-induced forming of oxide RRAM

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

Antenna assisted ReRAM formation

A semiconductor device includes a PCM stack that includes bottom electrode liner over a lower heater. The bottom electrode liner has a top-down view plus (+) geometry with a 'horizontal' portion being orthogonal to a ‘vertical’ portion. An airgap is formed within the PCM stack in an area located adjacent and between the ‘horizontal’ portion and the ‘vertical’ portion. The airgap has a substantially smaller dielectric constant than the surrounding PCM stack material(s). Therefore, the airgap may effectively reduce the amount of current that leaks from the PCM stack when flowing from the bottom electrode liner to a top contact or top electrode. Further, the airgap may allow for expansion of the surrounding PCM stack material(s) that may result from the heating of the PCM stack.

Phase change memory programming current leakage reduction

Arrays of PCM devices and techniques for fabrication thereof having an integrated resistor formed during heater patterning for uniform voltage drop amongst the PCM devices are provided. In one aspect, a PCM device includes: at least one PCM cell including a phase change material disposed on a heater; and at least one resistor in series with the at least one PCM cell, wherein the at least one resistor includes a same combination of materials as the heater. A memory array and a method of forming a PCM device are also provided.

Uniform voltage drop in arrays of memory devices

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

Semiconductor device identification using preformed resistive memory

Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a charge-particle-treated memory stack over the metal interconnect electrode. The charge-particle-treated memory stack includes a plurality of layers that includes a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode. The dielectric layer includes a portion of a blanket dielectric layer. The bottom electrode includes a portion of a blanket bottom electrode layer. The charge-particle-treated memory stack further includes a current-conducting filament characteristic that results from charge particle treatments applied while a top surface of the blanket dielectric layer is exposed and a top surface of the blanket bottom electrode is exposed.

Oxide-based resistive memory having a plasma-exposed bottom electrode

An apparatus comprising a dielectric layer located between a first electrode and a second electrode and a third electrode located on the dielectric layer between the first electrode and the electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

Horizontal RRAM device and architecture for variability reduction

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

Back end of line embedded RRAM structure with low forming voltage

Structures and methods are provided for integrating a resistance random access memory (ReRAM) in a back-end-on-the-line (BEOL) fat wire level. In one embodiment, a ReRAM device area contact structure is provided in the BEOL fat wire level that has at least a lower via portion that contacts a surface of a top electrode of a ReRAM device area ReRAM-containing stack. In other embodiments, a tall ReRAM device area bottom electrode is provided in the BEOL fat wire level and embedded in a dielectric material stack that includes a dielectric capping layer and an interlayer dielectric material layer.

BEOL fat wire level ground rule compatible embedded artificial intelligence integration

Techniques regarding quantum computer error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that interpolates a gate parameter associated with a target stretch factor from a reference model that includes reference gate parameters for a quantum gate calibrated at a plurality of reference stretch factors.

Stretch factor error mitigation enabled quantum computers

Techniques regarding calibrating one or more quantum decoder algorithms are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a correlation inversion decoder component that can calibrate a quantum decoder algorithm for decoding a quantum error-correcting code by estimating hyperedge probabilities of a decoding hypergraph that are consistent with a syndrome dataset.

Calibrated decoders for implementations of quantum codes

Growing community of inventors

Upper Saddle River, NJ, United States of America

Youngseok Kim