Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Globalfoundries Singapore Pte. Ltd.

Samsung Electronics Co., Ltd.

Globalfoundries Inc.

Freescale Semiconductor,inc.

Infineon Technologies North America Corp.

Globalfoundiers Singapore Pte. Ltd.

Young Way Teh

Wenhe Lin

Yong Meng Lee

Chung Woh Lai

John Leonard Sudijono

Liang Choo Hsia

Khee Yong Lim

Hui Peng Koh

Wee Leng Tan

Xiangdong Chen

Voon-Yew Thean

Christopher V Baiocco

Weipeng Li

Wenzhi Gao

Zhijiong Luo

Juan Boon Tan

Fan Zhang

Da Zhang

Bei Chao Zhang

Atul Champaklal Ajmera

Deleep R Nair

Yong Kong Siew

Vincent Ho

Haifeng Sheng

Haizhou Yin

Kern Rim

Brian Joseph Greene

Dae-Gyu Park

Yanxiang Liu

Elgin Kiok Boone Quek

Kenneth Jay Stein

Nivo Rovedo

Sunfei Fang

Jin-Ping Han

Jae Gon Lee

Siddhartha Panda

Min-Chul Sun

Anda C Mocuta

Jae-Eun Park

Michael Vincent Aquilino

Ja-hum Ku

Laegu Kang

Yun Ling Tan

Hung Y Ng

Melanie J Sherony

Jin Zheng Wallner

Bin Zhu

Jae-eon Park

Jun Jung Kim

Young Gun Ko

Jun-jung Kim

Vara Vakada

Arifuzzaman (Arif) Sheikh

Hao Zhang

Franck Arnaud

Jie Chen

Dae-Kwon Kang

Jinghong H (John) Li

Madhu Sudan Mukhopadhyay

Subramanian Sundareswara

Structures for a memory device and methods of forming a structure for a memory device. The structure includes a first and second source/drain regions in a semiconductor substrate, a first gate stack on the semiconductor substrate, and a second gate stack on the semiconductor substrate adjacent to the first gate stack. The first and second gate stacks are positioned in a lateral direction between the first source/drain region and the second source/drain region. The first gate stack includes first and second gate electrodes, and the first gate electrode includes segments spaced apart along a longitudinal axis of the first gate stack.

Flash memory devices with thickened source/drain silicide

A device includes a substrate with a device region surrounded by an isolation region, in which the device region includes edge portions along a width of the device region and a central portion. The device further includes a gate layer disposed on the substrate over the device region, in which the gate layer includes a graded thickness in which the gate layer at edge portions of the device region has a thickness Tthat is different from a thickness Tat the central portion of the device region.

High-K metal gate device

This application is directed to a semiconductor device with an oversized local contact as a Faraday shield, and methods of making such a semiconductor device. One illustrative device disclosed herein includes a transistor comprising a gate electrode and a source region, a source region conductor that is conductively coupled to the source region, a Faraday shield positioned above the source region conductor and the gate electrode and a first portion of a first primary metallization layer for an integrated circuit device positioned above and electrically coupled to the Faraday shield.

Semiconductor device with an oversized local contact as a Faraday shield

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Spacer-less low-K dielectric processes

Solutions for forming an integrated circuit structure having a substantially planar N-P step height are disclosed. In one embodiment, a method includes: providing a structure having an n-type field effect transistor (NFET) region and a p-type field effect transistor (PFET) region; forming a mask over the PFET region to leave the NFET region exposed; performing dilute hydrogen-flouride (DHF) cleaning on the exposed NFET region to substantially lower an STI profile of the NFET region; and forming a silicon germanium (SiGE) channel in the PFET region after the performing of the DHF.

Integrated circuit structure having substantially planar N-P step height and methods of forming

The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate.

Poly profile engineering to modulate spacer induced stress for device enhancement

Process for enhancing strain in a channel with a stress liner, spacer, process for forming integrated circuit and integrated circuit. A first spacer composed of an first oxide and first nitride layer is applied to a gate electrode on a substrate, and a second spacer composed of a second oxide and second nitride layer is applied. Deep implanting of source and drain in the substrate occurs, and removal of the second nitride, second oxide, and first nitride layers.

Spacer and process to enhance the strain in the channel with stress liner

An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

Balancing NFET and PFET performance using straining layers

An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors.

Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS

A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.

Method and apparatus for post silicide spacer removal

A semiconductor process and apparatus includes forming &#x3c;100&#x3e; channel orientation CMOS transistors () with enhanced hole mobility in the NMOS channel region and reduced channel defectivity in the PMOS region by depositing a first tensile etch stop layer () over the PMOS and NMOS gate structures, etching the tensile etch stop layer () to form tensile sidewall spacers () on the exposed gate sidewalls, and then depositing a second hydrogen rich compressive or neutral etch stop layer () over the NMOS and PMOS gate structures () and the tensile sidewall spacers (). In other embodiments, a first hydrogen-rich etch stop layer () is deposited and etched to form sidewall spacers () on the exposed gate sidewalls, and then a second tensile etch stop layer () is deposited over the NMOS and PMOS gate structures () and the sidewall spacers ().

Method for transistor fabrication with optimized performance

An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.

Integrated circuit system for suppressing short channel effects

A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200&#xb0; C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Dual stress memory technique method and related structure

A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends over a portion of the substrate a predetermined distance from a lateral edge of the L-shaped spacer. And removing oxide layers to expose the L-shape spacers.

Methods of forming semiconductor devices using embedded L-shape spacers

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Singapore, Singapore

Young Way Teh