Amkor Technology, Inc.

Utstarcom Korea Technologies Limited

Young Suk Chung

Jae Hak Yee

Jae Hun Ku

Jae Jin Lee

Sung Sik Jang

Jong Sik Paek

Seong Min Seo

Terry W Davis

Sang Hyun Ryu

Jae Sung Kwak

Chung Suk Han

Won Chul Do

Byung Hoon Ahn

Suk Gu Ko

Young Nam Choi

Hyung Ju Lee

Tae Heon Lee

Mu Hwan Seo

Doo Hyun Park

Jung Woo Lee

Tae Yong Lee

Jae Yoon Kim

Yoon Joo Kim

No Sun Park

Jae Beom Shim

Soo Jung Park

Ku Sun Hong

In one embodiment, an electronic device package structure includes an electronic die having conductive pads on one surface. The one surface is further attached to at least one lead. A conductive layer covers at least one conductive pad and at least portion of the lead thereby electrically connecting the lead to the conductive pad.

Electronic device package structure and method of fabricating the same

Metal leadframes, semiconductor packages made using the leadframes, and methods of making the leadframes and packages are disclosed. In one embodiment, the leadframe includes a rectangular frame. A chip pad and a plurality of leads are within the frame. The lower side of the chip pad and the leads includes one or more vertically recessed horizontal surfaces. The upper side of the chip pad may include a groove around a chip mounting region. In a package, the chip pad supports a semiconductor chip electrically connected to the leads. The lower side of the chip pad and leads are exposed at an exterior surface of the package body. Encapsulant material underfills the recessed lower surfaces of the chip pad and leads, thereby locking them to the encapsulant material. A wire may be reliably bonded to the chip pad within the groove formed in the upper side thereof.

Leadframe and semiconductor package made using the leadframe

A wafer level chip size package (WLCSP) and a method of manufacturing the same are disclosed. Lands are formed at the ends of redistribution layers. The redistribution layers excluding the lands and a first dielectric layer are covered with a second dielectric layer. After forming a first under bump metallurgy (UBM) layer on the land, a solder ball is reflowed to the first UBM layer. A second UBM layer is widely formed on the entire second dielectric layer that is the outer circumference of the first UBM layer and is connected to the redistribution layer through a via-hole. Therefore, the second UBM layer having a large area can be used as a ground plane or a power plane. In addition, the second UBM layer can electrically connect the redistribution layers physically separated from each other. Therefore, the plurality of redistribution layers can cross each other without being electrically shorted with each other.

Wafer level chip size package having redistribution layers

A semiconductor package has an insulative layer having at least one channel formed on a first surface thereof. A conductive pattern conforming to the at least one channel and exposed to a bottom surface of the semiconductor package is formed. A semiconductor die is electrically connected to the conductive patterns. An encapsulant is used to at least partially filling the at least one channel.

Semiconductor device having improved contact interface reliability and method therefor

A lead frame for making a semiconductor package is disclosed. The leadframe's leads include a lead lock provided at a free end of each inner lead that is adapted to increase a bonding force of the inner lead to a resin encapsulate, thereby effectively preventing a separation of the inner lead from occurring in a singulation process involved in the fabrication of the semiconductor package. A semiconductor package fabricated using the lead frame and a fabrication method for the semiconductor package are also disclosed. The lead frame includes a paddle, a plurality of tie bars for supporting the corners of the paddle, a plurality of leads arranged at each of four sides or two facing sides of the paddle in such a fashion that they are spaced apart from an adjacent side of the paddle while extending perpendicularly to the associated side of the paddle, each of the leads having lead separation preventing means adapted to increase a bonding force of the lead to a resin encapsulate subsequently molded to encapsulate the lead frame for fabrication of the semiconductor package, and dam bars for supporting the leads and the tie bars. Additional package embodiments include exposed protrusions extending downward from the leads. The exposed protrusions are irradiated with a laser to remove set resin prior to a solder ball attachment step.

Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant

Mobile phone

A semiconductor leadframe and a semiconductor package using same. More particularly, a semiconductor leadframe offering improved solder joint strength between a semiconductor package and a motherboard is disclosed. The leadframe comprises a plate-type frame body; a chip paddle on which a semiconductor chip may be mounted; a plurality of internal leads located radially and spaced at regular intervals about the perimeter of the chip paddle; external leads extending outward from the internal leads and with their terminals connecting to the frame body; and dam bars at the juncture of each external and internal lead for additional support and to ensure that the external leads remain exposed during subsequent encapsulation processes. The leadframe of the present invention providing additional solder joint strength through the use of internal leads having different lengths or surface areas.

Leadframe and semiconductor package with improved solder joint strength

Leadframe having lead locks to secure leads to encapsulant

A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Semiconductor package

Semiconductor packages are disclosed. An exemplary package includes horizontal leads each having a first side and an opposite second side. The second side includes a recessed horizontal surface. Two stacked semiconductor chips are within the package and are electrically interconnected in a flip chip style. One chip extends over the first side of the leads and is electrically connected thereto. The chips are encapsulated in a package body formed of an encapsulating material. The recessed horizontal surface of the leads is covered by the encapsulating material, and a portion of the second side of each lead is exposed at an exterior surface of the package body as an input/output terminal. A surface of one or both chips may be exposed. The stack of chips may be supported on the first side of the leads or on a chip mounting plate.

Semiconductor package including stacked chips with aligned input/output pads

A clamp and heat block assembly for wire bonding a semiconductor package assembly. The package assembly has a semiconductor chip having a plurality of bond pads on an upper surface the chip, a chip paddle secured to a bottom surface of the chip by an adhesive, a plurality of tie bars being connected to corners of the chip paddle and externally extending from the chip paddle, a plurality of leads radially formed at regular intervals along and spaced apart from the chip paddle and extending towards the chip paddle. The package assembly further includes a plurality of conductive wires electrically connected to the leads and the chip. The heat block assembly includes a heat block, a guide block, and a clamp. The guide block has a raised portion for receiving the heat block, which has a groove mating with the raised portion of the guide block. The guide block and heat block are secured to the package assembly by the clamp, which engages the package assembly on an upper surface of the leads. The clamp has a notch adapted to identify a first lead of the package assembly.

Clamp and heat block assembly for wire bonding a semiconductor package assembly

Growing community of inventors

Seoul, South Korea

Young Suk Chung