Samsung Electronics Co., Ltd.

Young-rae Park

Sang-rok Hah

Jung-Yup Kim

Bo-un Yoon

Hong-kyu Hwang

Chang-ki Hong

Kyung-Hyun Kim

Ho-Young Kim

Kwang-bok Kim

Jae-Phil Boo

Jong-won Lee

Jae-Dong Lee

Chang-Ki Hong

Jeong-sic Jeon

Jeong-heon Park

Jun-shik Bae

Gi-jong Park

Gee-won Nam

A slurry composition useful for chemical mechanical polishing of the surface of a material layer, e.g., a silicon oxide layer, is disclosed. A first material surface which is exposed to the slurry exhibits hydrophilicity, while a second material layer, e.g., a polysilicon layer, the surface of which is also exposed to the slurry, exhibits hydrophobicity, and accordingly acts as a polishing stopping layer. The slurry composition consists essentially of water, abrasive grains, and a polymer additive having both hydrophilic and hydrophobic functional groups.

Slurry for chemical mechanical polishing process and method of manufacturing semiconductor device using the same

A method for isolating SAC pads of a semiconductor device, including determining a chemical mechanical polishing process time necessary to isolate the SAC pads a desired amount by referring to a relationship equation between the extent of isolation of the self-aligned contact pads and the chemical-mechanical polishing process time. The chemical mechanical polishing process is performed for the determined process time on the semiconductor device to isolate the self-aligned contact pads the desired amount. The relationship equation is determined using a test semiconductor device.

Method for isolating self-aligned contact pads

A method of fabricating a contact pad of a semiconductor device is disclosed. The method includes forming a stopping layer over the semiconductor substrate. An interdielectric layer is formed over the stopping layer, and the interdielectric layer is planarized to expose at least a gate upper dielectric layer by using a material which exhibits a high-polishing selectivity with respect to the interdielectric layer. The interdielectric layer is etched in a region in which a contact pad will be formed on the semiconductor substrate. A conductive material is deposited on the semiconductor substrate. Finally, planarizing is carried out using a material which exhibits a high-polishing selectivity of the upper dielectric layer with respect to the conductive material.

Method for fabricating a contact pad of semiconductor device

A chemical mechanical polishing apparatus includes a polishing pad on which a wafer requiring planarization is placed, a conditioning disc having an abrasive surface for conditioning the polishing pad, a tank containing de-ionized water in which the conditioning disc soaks while standing by, and a cleaner for cleaning the conditioning disc. The conditioning disc cleaner is disposed in the tank of de-ionized water to remove polishing impurities from an abrasive surface of the conditioning disc. The cleaner may include a brush having bristles against which the abrasive surface of the conditioning disc is placed when it is lowered into the tank. In operation, after the wafer is polished, an abrasive surface of the conditioning disc is run over the upper surface of the polishing pad to condition the surface of the polishing pad. Then the conditioning disc is moved off of the upper surface of the polishing pad and to a stand-by position in which the abrasive surface of the disc is submerged in a liquid. Finally, while the conditioning disc is in its stand-by position, impurities are forced off of the abrasive surface and into the liquid by the cleaner disposed in the liquid. The conditioning disc is thus cleaned so that impurities are not transferred to the polishing pad during the next conditioning process.

Chemical mechanical polishing apparatus having a cleaner for cleaning a conditioning disc and method of conditioning a polishing pad of the apparatus

In method and apparatus for supplying a slurry for a chemical mechanical polishing (CMP) process, a slurry pre-treatment is provided for minimizing the size of abrasive particles in the slurry. In the slurry supplying method, after applying acoustic energy to the slurry to de-agglomerate agglomerated abrasive particles within the slurry, any remaining oversized abrasive particles having a diameter greater than a reference size are filtered out from the slurry. The acoustic energy application step and the filtering step are repeatedly performed for a predetermined time period while circulating the slurry. The slurry supplying apparatus includes a tank for holding a slurry, acoustic energy sources for applying acoustic energy to the slurry held within the tank, a slurry circulating line for circulating the slurry drawn out of the tank, which is connected to the tank, a filter for filtering out abrasive particle clumps having a diameter greater than a reference size from the slurry, which is disposed in the slurry circulating line, and a slurry supplying line for supplying the slurry from the slurry circulating line to a CMP equipment.

Method and apparatus for supplying chemical-mechanical polishing slurries

A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.

Semiconductor device including gate electrode having damascene structure and method of fabricating the same

An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

Methods of planarizing insulating layers on regions having different etching rates

A chemical mechanical polishing (CMP) process employs a ceria-based slurry as an abrasive. In particular, a nitride pattern is formed over a semiconductor substrate, and an oxide layer is then formed over the semiconductor substrate and the nitride pattern. Next, a sacrificial insulation layer which is devoid of surface steps is formed over the oxide layer. The sacrificial insulation layer and the oxide layer are then polished by CMP using the ceria-based slurry and using the nitride pattern as a stopper.

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Suwon, South Korea

Young-rae Park