Amkor Technology, Inc.

Korea Electronics Technology Institute

Young Kuk Park

Kwang Seok Oh

Jong Wook Park

Byoung Youl Min

Byung Joon Han

Jae Dong Kim

Kwang Ho Won

Hae Moon Seo

Myung Hyun Yoon

Jun Jae Yoo

A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Adhesive on wire stacked semiconductor package

Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventing damage. The stacking structure has a substrate formed with a plurality of circuit patterns; a first semiconductor chip bonded to an upper surface of the substrate and having a first plane and a second plane formed with a plurality of input/output pads; a spacer bonded to the second plane of the first semiconductor chip; a second semiconductor chip having first and second planes, the second plane being formed with a plurality of input/output pads, the first plane being provided with an insulating member so as to allow the second semiconductor chip to be bonded to the spacer, a first conductive wire for connecting the input/output pads of the first semiconductor chip to the circuit patterns of the substrate; and a second conductive wire for connecting the input/output pads of the second semiconductor chip to the circuit patterns of the substrate.

Method of forming a stacked semiconductor package

Disclosed herein is a multi-band ZigBee transceiver for supporting IEEE 802.15.4 wireless communications. In the multi-band ZigBee transceiver, a Multi-Mode Modem (MMM) selects any one of a European version standard using 860 MHz band, a US version standard using 920 MHz band, and a worldwide version standard using 2.4 GHz ISM band among IEEE 802.15.4 standards. A frequency synthesizing unit variably adjusts a carrier frequency according to the transmission standard. A transmission unit receives a digital modulated signal, low-pass-filters the digital modulated signal with a bandwidth thereof being variably adjusted, and up-converts the filtered digital modulated signal into an RF modulated signal corresponding to the selected transmission channel. A receiving unit down-converts the RF modulated signal into a BB modulated signal using the carrier frequency, low-pass-filters the BB modulated signal with a bandwidth thereof being variably adjusted according to the selected transmission standard, converts the filtered BB modulated signal into a digital modulated signal, and outputs the digital modulated signal to the MMM. A transmission/reception switch unit outputs the RF modulated signal, input from the transmission unit, to an antenna, or outputs the RF modulated signal, received from the antenna, to the receiving unit.

Multi-band ZigBee transceiver supporting IEEE 802.15.4 wireless communication

A wire bonding method for electrically interconnecting stacked semiconductor chips is disclosed. A substrate (e.g., printed circuit board or metal leadframe) is provided. Metal circuit patterns are provided outside of a chip mounting region of the substrate, and metal transfer patterns are provided proximate to the chip mounting region. Stacked semiconductor are disposed in the chip mounting region. Conductive wires are bonded between respective pads of one stacked chip and respective transfer patterns, and other conductive wires are bonded between respective pads of the other stacked chip and the same respective transfer patterns, thereby electrically connecting respective pads of the two chips through a pair of bond wires and an intermediate transfer pattern. The transfer patterns are separate from circuit patterns of the substrate. At least one of the first and second chips is electrically connected to some of the circuit patterns for external connection.

Wire bonding method for a semiconductor package

A semiconductor package including plural semiconductor chips, and a wire bonding step for electrically interconnecting the semiconductor chips, are disclosed. In an exemplary method, a substrate is provided. Conductive circuit patterns are provided outside of a chip mounting region of the substrate, and conductive transfer patterns are provided proximate to the chip mounting region. Chips are placed in the chip mounting region. Conductive wires are bonded between input/output pads of a first chip and respective transfer patterns, and other conductive wires are bonded between input/output pads of a second chip and the same transfer patterns, thereby electrically connecting respective input/output pads of the two chips through a pair of bond wires and an intermediate transfer pattern.

Growing community of inventors

Seoul, South Korea

Young Kuk Park