Infineon Technologies Ag

Other

International Business Machines Corporation

Siemens Aktiengesellschaft

Infineon Technologies North America Corp.

Young-Jin Park

Heon Lee

Gerhard Mueller

Carl John Radens

Ulrike Gruening

Johann Alsmeier

Jack Allan Mandelman

Byeong Yeol Kim

Gerhard Kunkel

Gangadhara Swami Mathad

Munir D Naeem

Rajiv M Ranade

Satish D Athavale

Brian S Lee

Brian J Lee

Kilho Lee

Young Limb

Elizabeth Morales

Stephan P Kudelka

Jai-hoon Sim

In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the AA and STI are different, the improvement comprising:

Method to etch poly Si gate stacks with raised STI structure

The invention describes the use of conductive lines having a non-rectangular shaped cross section to reduce line capacitance for a given pitch. Such conductive lines can reduce the height of integrated circuits with multi-level conductive lines without increasing line-to-line capacitance.

Multi-level conductive lines with reduced pitch

Sensing of information from a memory cell via a plateline is disclosed. The memory cell comprises a bitline coupled to a junction of a cell transistor while the other junction is coupled to an electrode of the capacitor. The bitline is coupled to a constant voltage source. A plateline is coupled to the other capacitor electrode.

Memory cell for plateline sensing

An integrated circuit having conductive lines with non-rectangular shaped cross-sections. The non-rectangular shaped cross-sections facilitate a reduction in line pitch without increasing capacitive coupling noise between adjacent conductive lines or, alternatively, reduction in capacitive coupling noise between adjacent lines for a given pitch.

Conductive lines with reduced pitch

A design layout for a memory cell structure is provided that achieves maximized channel length on the active areas, while not constricting the contact area of the capacitor contacts is provided. Specifically, the layout design provides a semiconductor memory structure that includes wordlines, bitlines, and sub-8F memory cells in a semiconductor substrate, said memory cells comprising a transfer gate transistor having a source region and a drain region formed in said substrate and a gate electrode, a memory cell stacked storage capacitor, a wordline conductor portion contacting said gate electrode, said wordline gate conductor portion forming part of one of said wordlines, a bitline contact to said source region, said bitline contact connecting said source region to one of said bitlines, and a capacitor contact between said capacitor and said drain region, wherein for at least one of said cells, said bitline contact and said capacitor contact are positioned at a distance from each other greater than from said bitline contact to a closest contact of another of said cells and greater than from said capacitor contact to a closest contact of another of said cells.

Design layout for a dense memory cell structure

A method for forming a transistor is formed where a gate electrode of the transistor is formed over a substrate defining a gate channel portion of the substrate. A mask is also formed over the substrate, a portion of the mask extending over a first portion of the substrate adjacent to the gate channel portion of the substrate. The mask defines a second portion of the substrate adjacent to the first portion of the substrate. An ion beam is directed toward the substrate to form a drain or a source region of said transistor adjacent to the gate channel portion of the substrate, the source or drain region including the first and second portions of the substrate. The ion beam implants the second portion of the substrate with a first implantation characteristic. The ion beam passes through the extended portion of the mask to reach the first portion to implant the first portion with a second implantation characteristic, such second implantation characteristic being different from the first implantation characteristic.

Self-aligned LDD formation with one-step implantation for transistor formation

A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures.

Method of reducing RIE lag for deep trench silicon etching

A method for forming self-aligned borderless contacts without a masking process, in accordance with the invention, includes forming a shallow trench isolation region about an active area region and forming a gate structure through the active area region. The gate structure and shallow trench isolation region extend above a surface of a substrate, and the substrate has an exposed portion of the between the gate structure and shallow trench isolation region. Undoped polysilicon is deposited over the gate structure, the shallow trench isolation region and the exposed portion of the substrate. The polysilicon is removed from the gate structure and shallow trench isolation region, and remaining polysilicon is doped to form contacts in contact with the substrate.

Maskless process for self-aligned contacts

Method to prevent oxygen out-diffusion from BSTO containing micro-electronic device

A memory cell, in accordance with the invention, includes a trench formed in a substrate, and an active area formed in the substrate below a gate and extending to the trench. The active area includes diffusion regions for forming a transistor for accessing a storage node in the trench, the transistor being activated by the gate. The gate defines a first axis wherein a portion of the active area extends transversely therefrom, the portion of the active area extending to the trench. The trench has a side closest to the portion of the active area, the side of the trench being angularly disposed relative to the gate such that a distance between the gate and the side of the trench is greater than a minimum feature size.

Memory cell layout for reduced interaction between storage nodes and transistors

Sensing of memory cell via a plateline

A method for forming a metalization system is provided. The method includes providing a substrate. A dielectric layer is formed over a surface of the substrate. A plurality of via holes is formed into a surface and the dielectric layer, such holes passing through the dielectric layer. Recesses are formed in the surface of the dielectric layer, such recesses terminating in a portion of the plurality of via holes passing through the dielectric layer. A metalization layer is deposited over the surface of the dielectric layer, portions of the metalization layer passing through the via holes, portions of the metalization layer being disposed in the recesses and portions of the metalization layer being disposed on the surface of the dielectric layer. The metalization layer is patterned into a plurality of conductors, one portion of the conductors being disposed on one level of the dielectric layer and another portion of the conductors disposed in the recesses. A metalization system having a substrate with a dielectric layer disposed over such substrate. A plurality of electrical conductors is provided, one portion of the conductors being disposed on one level of the dielectric layer and another portion of the conductors being recessed in a surface portion of the dielectric layer.

Growing community of inventors

Poughkeepsie, NY, United States of America

Young-Jin Park