Samsung Electronics Co., Ltd.

Young-Hoon Ro

Donghan Kim

Woo-Jae Kim

Heung-Kyu Kwon

Sung-Woo Park

Yun-Hyeok Im

Seung-Kon Mok

Jik-Ho Song

Ga-Young Kim

Jung-Hwan Chun

Embodiments of the inventive aspect include a printed circuit board and a semiconductor package using the same. The semiconductor package includes a substrate having one or more connection pads, semiconductor chips mounted on the substrate, an underfill layer filling a region between the semiconductor chips and the substrate, and solder bumps electrically connecting the connection pads and the semiconductor chips in the underfill layer. The substrate includes void preventing patterns protruding on a top surface of the substrate under the underfill layer.

Printed circuit board and semiconductor package using the same

A package on package structure is provided. The package on package structure may include a first substrate having a first center region and a first C-shaped edge region at a first end of the first center region. In example embodiments, the first C-shaped edge region may faun a first space. The package structure may further include at least two first connection pads on an inner surface of the first C-shaped edge region and the at least two first connection pads may be arranged to face one another. In example embodiments, at least one first solder ball may be arranged in the first space and the at least one first solder ball may be connected to the at least two first connection pads.

Package on package

A first semiconductor package includes a first substrate, a first semiconductor chip attached to the first substrate, an encapsulant which covers the first semiconductor chip, and conductive elastic members which are embedded in the encapsulant but with parts thereof exposed. A package on package (POP) includes the first semiconductor package and a second semiconductor package stacked in the first semiconductor package. The second semiconductor package includes a second substrate and a second semiconductor chip attached to the second substrate. The exposed parts of the elastic members are electrically connected to the second substrate. The encapsulant of the first package is formed by a molding process while the conductive elastic members are compressed within their elastic limit by the mold.

Helical springs electrical connecting a plurality of packages

A smart card is provided including a body with a cavity, an IC chip inserted into the cavity, and a universal PCB on which the IC chip can be mounted and electrically contacted regardless of its size, type and bonding structure. The universal PCB comprises groups of contact pads suitable for contacting IC chips of different sizes and designs.

Universal PCB and smart card using the same

A size reduced solid-state imaging apparatus may be provided. The solid-state imaging apparatus may include a wiring substrate having a body having a cavity on an area which a semiconductor chip may be mounted, a lead that may project inward into the cavity from the internal side of the body, and/or a tie bar.

Solid-state imaging apparatus, wiring substrate and methods of manufacturing the same

A semiconductor package including a dam and a method for fabricating the same are provided. The semiconductor package comprises a package substrate, a semiconductor chip attached to the substrate, a TIM formed on the semiconductor chip, a dam that substantially surrounds the TIM, and a lid placed over the TIM to contact a surface thereof. Thus, a TIM can be prevented from flowing down from the original position at high temperatures. Therefore, the performance of the semiconductor package does not deteriorate even at high temperatures.

Semiconductor package having dam and method for fabricating the same

A semiconductor chip package comprising a chip with a lid having venting holes hermetically sealed with screws and a manufacturing method thereof are provided. The semiconductor chip package of the present invention comprises a chip such as a central processing unit (CPU) chip generating a large amount of heat; a substrate having upper and lower surfaces, the chip attached to the upper surface of the substrate; external connection terminals extending from the lower surface of the substrate and electrically connected to the chip; a lid attached to the upper surface of the substrate. The lid has a cavity for receiving the chip on a lower surface and venting holes penetrating the lid. The package includes sealing screws for hermetically sealing the venting holes. With the present invention, the venting holes formed through the lid are hermetically sealed without creating any voids or cracks in the sealant as in the prior art.

Growing community of inventors

Hwaseong-si, South Korea

Young-Hoon Ro