Apple Inc.

Young Doo Jeon

Jun Zhai

Chih-Ming Chung

Yifan Kao

Taegui Kim

Shawn Searles

Vidhya Ramachandran

Chonghua Zhong

Jun Chung Hsu

Huabo Chen

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

Semiconductor packaging substrate fine pitch metal bump and reinforcement structures

A system that includes an integrated circuit die and a power supply decoupling unit is disclosed. The system includes an integrated circuit die, and interconnection region, and a decoupling unit. The integrated circuit die includes a plurality of circuits, which each include multiple devices interconnected using wires fabricated on a first plurality of conductive layers. The interconnection region includes multiple solder balls, and multiple conductive paths, each of which includes wires fabricated on a second plurality conductive layers. At least one solder ball is connected to an Input/Output terminal of a first circuit of the plurality of circuits via one of the conductive paths. The decoupling unit may include a plurality of capacitors and a plurality of terminals. Each terminal of the decoupling unit may be coupled to a respective power terminal of a second circuit of the plurality of circuits via the conductive paths.

Integrated circuit die decoupling system with reduced inductance

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San Jose, CA, United States of America

Young Doo Jeon