Semiconductor Manufacturing International (Beijing) Corporation

Semiconductor Manufacturing International (Shanghai) Corporation

Semiconductor Manufacturing International Corp.

Youfeng He

Fumitake Mieno

Xiaopeng Yu

Zhengling Chen

A method is provided for fabricating fin field-effect transistors. The method includes providing a substrate. The method also includes forming a plurality of fins on a surface of the substrate. Further the method includes forming a transitional layer having atoms identical to atoms of the fins on side and top surfaces of the plurality of fins by a deposition process. Further, the method also includes performing an oxidation process to convert the transitional layer and a surface portion of the fins into a dielectric material to form a gate dielectric layer on the plurality of fins.

Fin field-effect transistor

Fin field-effect transistor and fabrication method thereof

The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, a plurality of peripheral shallow trench isolation (STI) units in the peripheral substrate, and at least one MOS transistor on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, a plurality of vertical LEDs on the N-type ion buried layer, a plurality of storage shallow trench isolation (STI) units between the vertical LEDs, and a plurality of phase change layers on the vertical LED and between the storage STI units. The storage STI units have thickness substantially equal to thickness of the vertical LEDs. The peripheral STI units have thickness substantially equal to thickness of the storage STI units. The N-type conductive region contains SiC. A top of P-type conductive region is flush with a top of the peripheral substrate. The N-type conductive region containing SiC reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

Phase change memory

A semiconductor device and a method for forming the same are provided. The method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.

Semiconductor device

A method for forming a semiconductor device is provided. The exemplary method includes: providing a substrate having a gate structure and first spacers on both sidewalls of the gate structure formed on a top surface of the substrate; forming first openings in the substrate by using the first spacers as a mask, wherein the first openings are located on both sides of the gate structure; forming second openings by etching the first openings with an etching gas, wherein each of the second openings is an expansion of a corresponding one of the first openings toward the gate structure and extends to underneath an adjacent first spacer; and forming epitaxial layers in the first openings and the second openings.

Method for forming semiconductor device

Phase change memory and method for fabricating the same

The invention provides a phase change memory and a method for forming the phase change memory. The phase change memory includes a storage region and a peripheral circuit region. The peripheral circuit region has a peripheral substrate, peripheral shallow trench isolation (STI) units in the peripheral substrate, and MOS transistors on the peripheral substrate and between the peripheral STI units. The storage region has a storage substrate, an N-type ion buried layer on the storage substrate, vertical LEDs on the on the N-type ion buried layer, storage shallow trench isolation (STI) units between the vertical LEDs, and phase change layers on the vertical LEDs and between the storage STI units. The storage STI units have thickness equal to thickness of the vertical LEDs. Each vertical LED comprises an N-type conductive region on the N-type ion buried layer, and a P-type conductive region on the N-type conductive region. The P-type conductive region contains SiGe. The peripheral STI units have thickness equal to thickness of the storage STI units. A top of P-type conductive region is flush with a top of the peripheral substrate. The P-type conductive region containing SiGe reduces drain current through the vertical LED and raises current efficiency of the vertical LED. The peripheral circuit region can work normally without adverse influence on performance of the phase change memory.

Growing community of inventors

Shanghai, China

Youfeng He