Stats Chippac Pte. Ltd.

Orthodyne Electronics Corporation

You Yang Ong

Seng Guan Chow

Dioscoro A Merilo

Heap Hoe Kuan

Ma Shirley Asoy

Wai Kwong Tang

Kuan Ming Kan

Larry Lewellen

Zurina Binti Zukiffly

Saat Shukri Bin Embong

Christoph Benno Luechinger

Garrett Leigh Wong

Cheong Chiang Ng

Suhairi Mohmad

Kwang Yong Chung

Mohd Helmy Bin Ahmad

A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.

Stacked integrated circuit package system

An embedded integrated circuit package-on-package system is provided forming a first integrated circuit package system, forming a second integrated circuit package system, and mounting the second integrated circuit package system over the first integrated circuit package system with the first integrated circuit package system, the second integrated circuit package system, or a combination thereof being an embedded integrated circuit package system or an embedded stacked integrated circuit package system.

Embedded integrated circuit package-on-package system

A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.

Thermally enhanced semiconductor package system

A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.

Hyper thermally enhanced semiconductor package system comprising heat slugs on opposite surfaces of a semiconductor chip

An integrated circuit package system includes a conductive substrate. A heat sink and a plurality of leads are etched in the substrate to define a conductive film connecting the heat sink and the plurality of leads to maintain their spatial relationship. A die is attached to the heat sink and wire bonded to the plurality of leads. An encapsulant is formed over the die, the heat sink, and the plurality of leads. The conductive film is etched away to expose the encapsulant and the bottom surfaces of the heat sink and the plurality of leads. Wave soldering is used to form solder on at least the plurality of leads. Multiple heat sinks and hanging leads are provided.

Integrated circuit package system using etched leadframe

A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Method of manufacturing non-leaded integrated circuit package system having etched differential height lead structures

A method of manufacture of an embedded integrated circuit package system includes: forming a first conductive pattern on a first structure; connecting a first integrated circuit die, having bumps on a first active side, directly on the first conductive pattern by the bumps; forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern; forming a channel in the substrate forming encapsulation; and applying a conductive material in the channel.

Embedded integrated circuit package system and method of manufacture thereof

An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.

Integrated circuit package-on-package stacking system

An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.

Embedded integrated circuit package system

An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.

Integrated circuit package-on-package stacking system and method of manufacture thereof

The present invention provides a method of making a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.

Stackable power semiconductor package system

The present invention provides a thermally enhanced power semiconductor package system comprising providing a power semiconductor die, forming an upper lead frame on the power semiconductor die and forming a lower lead frame below the power semiconductor die, wherein the upper lead frame and the lower lead frame are provided in an offset configuration relative to each other to provide two heat dissipation paths.

Thermally enhanced power semiconductor package system

An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.

An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device.

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Singapore, Singapore

You Yang Ong