Fujitsu Corporation

Fujitsu Semiconductor Limited

Kyushu Fujitsu Electronics Limited

Fujitsu Automation Limited

Other

Socionext Inc.

Kyushu Fujitsu Elecronics Limited

Yoshiyuki Yoneda

Kazuto Tsuji

Junichi Kasai

Hideharu Sakoda

Ryuji Nomoto

Masanori Onodera

Toshimi Kawahara

Seiichi Orimo

Hirohisa Matsuki

Eiji Watanabe

Mitsutaka Sato

Masaharu Minamizawa

Yukio Saigo

Shigeyuki Maruyama

Kenichi Nagashige

Atsushi Kikuchi

Toshio Hamano

Tetsuya Fujisawa

Masashi Takenaka

Yoshihiro Kubota

Masao Sakuma

Nobutaka Shimizu

Norio Taniguchi

Takashi Mashiko

Kazuhiro Tashiro

Michio Sono

Makoto Haseyama

Kazuyuki Imamura

Toshiyuki Motooka

Takashi Hozumi

Tetsurou Honda

Kenji Itasaka

Terumi Kamifukumoto

Yasuyuki Itoh

Takanori Watanabe

Yasuhiro Shinma

Toshiyuki Honda

Norio Fukasawa

Yoshitaka Aiba

Ichiro Yamaguchi

Yoshihiko Ikemoto

Masaki Waki

Mitsunada Osawa

Yuzo Hamanaka

Tadahiro Okamoto

Kaname Ozawa

Naomi Miyaji

Michio Hayakawa

Akihiro Oku

Nobukatsu Saito

Yasunori Fujimoto

Muneharu Morioka

Masaru Nukiwa

Shinya Nakaseko

Mamoru Suwa

Fumitoshi Fujisaki

Shinichiro Maki

Shinsuke Nakajyo

Osamu Yamaguchi

Takumi Ihara

Koichi Nakamura

Syuichi Monma

Masafumi Tetaka

Ryuuji Nomoto

Yukihiro Kuriki

Masaki Uchida

Nobuo Ohyama

Akihiro Shigeno

Ryoichi Yokoyama

Masao Fukunaga

A semiconductor device is disclosed that includes a support substrate, a first semiconductor element that is mounted on one side of the support substrate, a second semiconductor element including a high frequency electrode that is mounted on the one side of the support substrate, a via hole that is provided at the support substrate in relation to the high frequency electrode, and an external connection electrode that is provided on the other side of the support substrate in relation to the via hole.

Semiconductor device having a high frequency external connection electrode positioned within a via hole

Disclosed is a semiconductor device including first and second semiconductor elements, first and second external connection terminals and a sealing member. The first external connection terminal is provided at a first surface of the first semiconductor element. The second semiconductor element is provided at a second surface side, that is at a side opposite to the first surface, of the first semiconductor element. The second external connection terminal is connected to the second semiconductor element, and the second external connection terminal is configured to be, together with the first external connection terminal, connected to a wiring board. The sealing member seals the first and second semiconductor elements and exposes a portion, that is configured to be connected to the wiring board, of the first external connection terminal and a portion, that is configured to be connected to the wiring board, of the second external connection terminal.

Encapsulated semiconductor chips with wiring including controlling chip and method of making the same

A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts.

Method of testing a semiconductor device and suctioning a semiconductor device in the wafer state

A semiconductor device of the invention includes a substrate in which a power-supply electrode and a ground electrode are provided. A first semiconductor chip is disposed over the substrate and has a first conductor layer formed on a surface facing a second semiconductor chip. A second conductor layer is disposed over the first semiconductor chip and has a second conductor layer formed on a surface facing the first semiconductor chip. And an adhesive layer is disposed between the first conductor layer and the second conductor layer and bonds together the first semiconductor chip and the second semiconductor chip. In the semiconductor device, the adhesive layer and the first and second conductor layers function as a capacitor.

Adhesive layer forming a capacitor dielectric between semiconductor chips

A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.

Semiconductor device and manufacturing method thereof

A method of design of a circuit board enabling high density conductor lines to be drawn efficiently. A rats nest is formed by connecting pads to which terminals of an electronic device are connected and external connection terminals by lines. A region with the highest density of lines of the rats nest is then selected and design rules relating to routes and dimensions of conductor lines are set in the region with the highest density of lines of the rats nest. Conductor lines are then laid at the region with the highest density of lines of the rats nest, and whether or not the conductor lines can be laid at the region with the highest density of lines of the rats nest is confirmed. Setting of the design rules and laying of conductor lines are if the conductor lines cannot be laid, and the conductor lines of the remaining regions are laid by the set design rules if the conductor lines can be laid.

Method of designing circuit board

A device including a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic film.

Device having resin package and method of producing the same

Semiconductor device having an alignment mark formed by the same material with a metal post

A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.

Manufacturing method of a semiconductor device incorporating a passive element and a redistribution board

A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

Method of forming a device substrate and semiconductor package including a pyramid contact

Semiconductor device and package including forming pyramid mount protruding through silicon substrate

Growing community of inventors

Kawasaki, Japan

Yoshiyuki Yoneda