Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Renesas Electronics Corporation

Yoshiyuki Ishigaki

Masahiro Ishida

Hiroki Honda

Shigeki Ohbayashi

Hirotada Kuriyama

Motomu Ukita

Kimiharu Uga

Kazuhito Tsutsumi

Hidemoto Tomita

Yasuhiro Fujii

Shigenobu Maeda

Toshiaki Iwamatsu

Takashi Ipposhi

Shigeto Maegawa

Yukio Maki

Toshiaki Tsutsumi

Il-Jung Kim

Takahiro Yokoyama

Tsuyoshi Koga

Tomohiro Hosokawa

Motoi Ashida

Takashi Terada

Takashi Izutsu

Yasuichi Masuda

Yasushi Nakashima

Makoto Dei

In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be superimposed on a dummy element formation region in a two-dimensional view. In a first interlayer insulating film and a second interlayer insulating film covering the memory cell transistor, a contact plug is formed to penetrate the first interlayer insulating film and a via is formed to penetrate a second interlayer insulating film.

Semiconductor device

A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element, a second gate wiring element, a first connector, and a second connector. Each memory cellhas first and second sets having a driver transistor, a load transistor, and an access transistor. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

Semiconductor storage device and method of fabricating the same

Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (), a channel () and a source () are integrally formed on a surface of a second oxide film () by polysilicon. The drain () is formed to be connected with a pad layer () (second polycrystalline semiconductor layer) through a contact hole () which is formed to reach an upper surface of the pad layer (). The pad layer () positioned on a bottom portion of the contact hole () (opening) is provided with a boron implantation region BR.

Thin-film transistor and method of fabricating the same

A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMQS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at most 1.2 times longer than the gate width of first and second access nMOS transistors.

Semiconductor memory device with reduced memory cell area

A CMOS-SRAM has a plurality of full CMOS type memory cells () and a capacity plate (). The memory cells () are two-dimensionally arranged in the row direction and in the column direction. The capacity plateadds an additional capacity to nodes NDand NDfor storing data in order to reduce soft errors. The capacity plate () is common with the plurality of memory cells (). The capacity plates () are separated by every column, that is in the row direction. The capacity plate () is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell () of a certain column, the memory cell () is replaced with a redundant memory cell.

Semiconductor memory device having a capacitive plate to reduce soft errors

A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.

Semiconductor memory device

A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T . At least a portion of the latch circuit is formed above the bit line.

Semiconductor memory device having a latch circuit and storage capacitor

A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element , a second gate wiring element , a first connector , and a second connector . Each memory cell has first and second sets having a driver transistor , a load transistor , and an access transistor . The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.

An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.

Static semiconductor memory device

A semiconductor memory having: a full CMOS-type of memory cell ( ) including an n-type bulk access transistor ( ), an n-type bulk driver transistor ( ) and a p-type bulk load transistor ( ) by twos, and a charge capacitance adding charge capacitor element ( ) connected to cell nodes (N N ) in order to secure a soft error resistance. In the semiconductor memory, an insulating film ( ) and a conductive film ( ) are directly formed on each upper side of first and second cell nodes (N N ) for constituting a charge capacitor element ( ) for adding a charge capacitance. The insulating film ( ) is held between the cell node (N N ) and the conductive film ( ), covering both first and second cell nodes (N N ) in common.

Semiconductor memory

A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

Growing community of inventors

Tokyo, Japan

Yoshiyuki Ishigaki