Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Yoshito Ikeda

Kaoru Inoue

Katsunori Nishii

Yutaka Hirose

Hiroyuki Masato

Toshinobu Matsuno

Tsuyoshi Tanaka

Daisuke Ueda

Yasuhiro Uemoto

Tomohiro Murata

Takahiko Murata

Takumi Yamaguchi

Shinji Yoshida

Shigetaka Kasuga

Hiroyuki Sakai

Akiyoshi Tamura

Takayuki Yoshida

Yorito Ohta

Katsunori Nishi

A semiconductor device has a Group III nitride semiconductor layer and a gate electrode formed on the Group III nitride semiconductor layer. The gate electrode contains an adhesion enhancing element. A thermally oxidized insulating film is interposed between the Group III nitride semiconductor layer and the gate electrode.

Semiconductor device and method for fabricating the same

The semiconductor device of this invention includes an active region formed from a group III nitride semiconductor grown on a substrate and an insulating oxide film formed in a peripheral portion of the active region by oxidizing the group III nitride semiconductor. On the active region, a gate electrode in Schottky contact with the active region extending onto the insulating oxide film and having an extended portion on the insulating oxide film is formed, and ohmic electrodes respectively serving as a source electrode and a drain electrode are formed with space from side edges along the gate length direction of the gate electrode.

Method of fabricating a semiconductor device

A semiconductor device has an active region composed of a group III-V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

Method for fabricating a semiconductor device for reducing a surface potential

A semiconductor device has: a buffer layer formed on a conductive substrate and made of AlGaN with a high resistance; an element-forming layer formed on the buffer layer, having a channel layer, and made of undoped GaN and N-type AlGaN; and a source electrode, a drain electrode and a gate electrode which are selectively formed on the element-forming layer. The source electrode is filled in a through hole provided in the buffer layer and the element-forming layer, and is thus electrically connected to the conductive substrate.

Semiconductor device including a group III-V nitride semiconductor

An infrared sensor includes a series capacitor element and a reference capacitor element each exhibiting a predetermined capacitance value; an infrared-detecting capacitor element whose capacitance value varies depending on an intensity of infrared light incident on the element; and an output node being a node at which a first terminal of the series capacitor element, a first terminal of the reference capacitor element and a first terminal of the infrared-detecting capacitor element are connected to one another. The intensity of infrared light is output as a potential difference between the reference potential which is brought to a potential by applying a predetermined voltage between the series capacitor element and the reference capacitor element and the detection potential which is brought to a potential by applying a predetermined voltage between the series capacitor element and the infrared-detecting capacitor element.

Infrared sensor and infrared sensor array

Method for fabricating a semiconductor device including a group III nitride semiconductor

An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Semiconductor device having an active region formed from group III nitride

A semiconductor device has an active region composed of a group III&#x2013;V nitride semiconductor and ohmic electrodes and a gate electrode each formed on the active region. The active region has an entire surface thereof exposed to a plasma such that a surface potential for electrons therein is lower than in the case where the entire surface is not exposed to the plasma.

Method for fabricating a semiconductor device including exposing a group III-V semiconductor to an ammonia plasma

A buffer layer, an undoped gallium nitride layer, and an n-type gallium nitride active layer are formed on a sapphire substrate. Ohmic contacts and a Schottky contact are then formed on the n-type gallium nitride active layer as a source contact, a drain contact and a gate contact, respectively. The Schottky contact is a copper alloy, such as palladium copper, in which the content by weight of copper is 5%.

Gallium nitride compound semiconductor device having schottky contact

Field effect transistor semiconductor device

A semiconductor device has a first semiconductor layer composed of a group III&#x2013;V nitride, an oxide film formed by oxidizing a second semiconductor layer composed of a group III&#x2013;V nitride to be located on the gate electrode formation region of the first semiconductor layer, an insulating film formed on the oxide film to have a composition different from the composition of the oxide film, and a gate electrode formed on the insulating film.

In a method for fabricating a semiconductor device, a first semiconductor layer of aluminum gallium nitride is first formed on a substrate, and a protection film containing silicon is then formed on the first semiconductor layer in such a manner that a device-isolation region is uncovered. Thereafter, the method further includes the step of heat-treating the first semiconductor layer in an oxidizing atmosphere whose temperature is adjusted to be within a range of 950&#xb0; C. or more and 1050&#xb0; C. or less.

Method for fabricating semiconductor device

The semiconductor device of the present invention includes: a gallium nitride (GaN) compound semiconductor layer; and a Schottky electrode formed on the GaN compound semiconductor layer, wherein the Schottky electrode contains silicon.

Growing community of inventors

Osaka, Japan

Yoshito Ikeda