Kabushiki Kaisha Toshiba

Tokyo Electron Limited

Kabushiki Kaisha Tohisba

Yoshitaka Tsunashima

Ichiro Mizushima

Masayuki Tanaka

Shigehiko Saida

Kiyotaka Miyano

Yoshio Ozawa

Tsutomu Sato

Kyoichi Suguro

Seiji Inumiya

Yuuichi Mikata

Yasumasa Suizu

Katsuya Okumura

Yasushi Akasaka

Kazuhiro Eguchi

Haruo Okano

Takashi Nakao

Kouji Matsuo

Moto Yabuki

Shigeru Kambayashi

Takako Okada

Shinji Onga

Jun-ichi Shiozawa

Shinichi Takagi

Atsushi Yagishita

Akihito Yamamoto

Mie Matsuo

Toshihiko Iinuma

Tsunetoshi Arikado

Takayuki Hiraoka

Mitsuhiro Noguchi

Takayuki Ito

Katsuhiko Hieda

Kazuaki Nakajima

Tomohiro Saito

Yuichiro Mitani

Yukihiro Ushiku

Akira Goda

Ryota Fujitsuka

Takeo Maeda

Kikuo Yamabe

Takeo Furuhata

Junichiro Iba

Tetsuya Kai

Hiroshi Gojohbori

Takeshi Hamamoto

Kazuhide Hasebe

Takashi Suzuki

Katsuyuki Sekine

Masahiro Kiyotoshi

Keitaro Imai

Hirofumi Inoue

Tomonori Aoyama

Atsushi Murakoshi

Kenji Todori

Akio Kaneko

Hiroshi Akahori

Motoyuki Sato

Takuya Sugawara

Shinji Miyazaki

Osamu Arisumi

Yuichiro Morozumi

Hirokazu Ishida

Masaki Kamimura

Dong-Kyun Choi

Shuji Katsui

Keisaku Yamada

Hideichi Kawaguchi

Takako Kashio

Seiji Ihumiya

Kyoioni Suguro

Shigeru Yonemoto

Hexachlorodisilane (SiCl) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.

Semiconductor memory device and method of manufacturing the same

A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.

Method for manufacturing thin film

Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

Semiconductor device having a gate insulating film structure including an insulating film containing metal, silicon and oxygen and manufacturing method thereof

A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

Semiconductor device and method for manufacturing the same

A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

Semiconductor device and method for manufacturing semiconductor device

A method of manufacturing a semiconductor device includes forming a dummy gate wiring layer having a side surface and an upper surface on a first area of one major surface of a substrate, the major surface of the substrate including the first area and a second area, thereafter, forming a semiconductor film on the second area of the major surface of the substrate by using epitaxial growth, the semiconductor film having a thickness smaller than a thickness of the dummy gate wiring layer, and forming, on the semiconductor film, a gate sidewall which is made of an insulator and covers the side surface of the dummy gate wiring layer.

Method of manufacturing semiconductor device using dummy gate wiring layer

A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

Semiconductor device having an element isolating insulating film

A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

Semiconductor device and method of manufacturing the same by filling a trench which includes an additional coating step

To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Method for fabricating a localize SOI in bulk silicon substrate including changing first trenches formed in the substrate into unclosed empty space by applying heat treatment

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a silicate film containing metal on a substrate; and introducing nitrogen and deuterium into the silicate film by using NDgas.

Semiconductor device and manufacturing method of the same

A method of manufacturing a MOS transistor incorporating a silicon oxide film serving as a gate insulating film and containing nitrogen and a polycrystalline silicon film serving as a gate electrode and containing a dopant and arranged such that the gate electrode is formed on the gate electrode insulating film, and an oxidation process using ozone is performed to sufficiently round the shape of the lower edge of the gate electrode.

Semiconductor device and method of manufacture thereof

Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

Growing community of inventors

Yokohama, Japan

Yoshitaka Tsunashima