Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Yoshiro Shimojo

Yoshinori Kumura

Yasuhito Yoshimizu

Shinya Arai

Tohru Ozaki

Iwao Kunishima

Susumu Shuto

Ryota Katsumata

Keisuke Nakatsuka

Tetsuaki Utsumi

Yoshitaka Kubota

Masaru Kito

Hiroyuki Kanaya

Tomoya Sanuki

Masahisa Sonoda

Yoshihiro Yanai

Tsuneo Uenaka

Kazuharu Yamabe

Toru Ozaki

A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.

Semiconductor storage device

A semiconductor storage device includes a first stacked body including first insulating films and first conductive films that are alternately stacked in a first direction. A first columnar body and a second columnar body extend within the first stacked body in the first direction. A second conductive film is provided above the first stacked body, and extends in a third direction intersecting the first direction and the second direction. A third insulator is adjacent to the second conductive film and extends in the third direction. A third conductive film is adjacent to the third insulator and extends in the third direction. A third columnar body is provided on the first columnar body. A fourth columnar body is provided on the second columnar body. A thickness of a third semiconductor portion in the first direction is greater than a thickness of the second conductive film in the first direction.

Semiconductor storage device with improved cutoff characteristics

In a method for manufacturing a memory, a first stacked body is formed by stacking a first insulating film and a first sacrificial film. A first columnar body including a first semiconductor portion extending in the first stacked body in the first direction and a charge trapping film provided on an outer peripheral surface of the first semiconductor portion is formed. A second columnar body provided in a second direction of the first columnar body and including a second semiconductor portion stretching in the first stacked body in the first direction and a charge trapping film on an outer peripheral surface of the second semiconductor portion is formed. A second insulating film is formed above the first stacked body. A third columnar body including a third semiconductor portion provided on both the first columnar body and the second columnar body and stretching in the second insulating film in the first direction and a first gate insulating film provided on an outer peripheral surface of the third semiconductor portion is formed. A first division insulating film extending in the first direction and a third direction intersecting the first direction and the second direction and dividing the third semiconductor portion of the third columnar body in the second direction is formed.

Method for manufacturing a semiconductor storage device including a division film

According to one embodiment, a stacked body includes a plurality of electrode layers stacked with an insulator interposed. A conductive via pierces the stacked body, and connects an upper layer interconnect and a lower layer interconnect. A insulating film is provided between the via and the stacked body. A distance along a diametral direction of the via between a side surface of the via and an end surface of one of the electrode layers opposing the side surface of the via is greater than a distance along the diametral direction between the side surface of the via and an end surface of the insulator opposing the side surface of the via.

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

Semiconductor memory device including a substrate, various interconnections, semiconductor member, charge storage member and a conductive member

According to one embodiment, a semiconductor memory device includes: a first interconnect layer including a first electrode that extends in a first direction and a second electrode that extends in a second direction and is in contact with one end of the first electrode; a second interconnect layer including a third electrode that is provided adjacently to the first electrode and a fourth electrode that is in contact with one end of the third electrode; a first semiconductor layer provided between the first electrode and the third electrode; a first charge storage layer provided between the first semiconductor layer and the first electrode; a second charge storage layer provided between the first semiconductor layer and the third electrode; and a first bit line provided above the first semiconductor layer and extending in the first direction.

Semiconductor memory device

A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Memory device

A semiconductor memory device according to an embodiment includes: first and second memory columnar bodies aligned in a second direction intersecting a first direction, the first and second memory columnar bodies respectively including a semiconductor layer and extending in the first direction; a bit line disposed above the first and second memory columnar bodies; and a first connecting line disposed between the first and second memory columnar bodies and the bit line in the first direction and electrically coupled to the semiconductor layers of the first and second memory columnar bodies and the bit line, the first connecting line extending linearly in the second direction, and a center line widthwise of the first connecting line being in a position displaced in a third direction, the third direction intersecting the first and second directions, from positions of centers of the first and second memory columnar bodies.

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Yokkaichi, Japan

Yoshiro Shimojo